Firestorm: FMLA (by element, 4S) measurements

Code:

  fmla v0.4s, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	2	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	3	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	84	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	90	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.4s, v1.4s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	c9	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10205	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	104	10444	500	5706908	40123	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	4	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	0	0	710	0	2	41	2	3	39479	0	10000	100	40038	40084	40146	40038	40038
10204	40037	309	0	1	0	0	0	0	0	61	39407	25	10100	100	10000	110	10000	516	5708304	40018	0	40037	40037	38108	0	25	38745	10100	200	10164	212	30000	40037	40084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	741	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	312	0	1	0	0	0	0	0	1037	39407	25	10100	100	10000	100	10000	500	5706908	40088	3	40037	40037	38115	0	3	38745	10100	200	10000	200	30498	40183	40084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	734	0	2	16	2	2	39479	7	10000	100	40038	40038	40038	40038	40075
10204	40180	312	0	1	0	0	0	0	0	61	39407	25	10100	103	10018	100	10000	500	5706908	40018	0	40037	40037	38108	0	3	38745	10100	202	10174	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	0	0	0	0	0	0	740	0	2	16	2	2	39479	0	10000	100	40038	40038	40086	40038	40038
10204	40037	300	0	0	0	1	0	0	0	61	39407	25	10100	104	10018	100	10000	546	5706908	40018	0	40037	40037	38108	0	7	38800	10100	200	10000	204	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	0	0	0	0	0	1065	39407	86	10100	100	10000	104	10296	500	5706908	40018	0	40037	40037	38108	0	3	38763	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	2	1	0	0	0	0	0	1	710	1	2	40	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40084	304	0	1	0	4	0	0	0	2916	39407	83	10100	100	10000	109	10000	500	5711096	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	6	0	0	0	0	740	1	3	17	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40228	311	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	522	5706908	40018	0	40178	40084	38108	0	3	38745	10100	200	10160	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	4	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39621	0	10000	100	40038	40038	40038	40086	40038
10204	40037	300	1	0	0	0	156	0	0	814	39407	25	10100	113	10000	100	10000	500	5708304	40018	0	40084	40037	38108	0	3	38745	10250	200	10000	200	30000	40037	40037	1	1	10202	100	99	100	100	10000	100	0	0	0	7	0	0	4	0	0	0	710	1	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40086
10204	40037	300	0	0	0	0	396	0	1	61	39407	25	10100	110	10000	100	10000	500	5711096	40018	0	40037	40037	38118	0	16	38745	10100	200	10499	200	30000	40084	40179	1	1	10201	100	99	100	100	10000	100	0	0	2	2	0	3	2	0	0	0	710	1	3	16	2	3	39479	3	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40084	300	0	0	0	1	1	3	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	0	8	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40177	317	0	0	0	0	0	0	537	0	61	39389	25	10010	10	10000	10	10000	50	5706908	1	40018	3	40037	40037	38130	0	7	38767	10010	22	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	5	0	7203	0	0	640	2	16	3	3	39473	0	10000	10	40038	40085	40038	40038	40229
10024	40037	300	1	0	0	0	0	0	21	0	61	39407	25	10010	10	10018	10	10148	61	5706908	1	40018	3	40037	40037	38130	0	3	38767	10010	20	10000	22	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	6	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40180	313	0	0	0	0	3	0	405	0	296	39407	25	10010	10	10018	10	10000	50	5706908	1	40018	0	40037	40037	38130	0	3	38767	10454	20	10000	20	30000	40037	40085	4	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	664	5	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40180
10024	40037	312	0	0	0	0	0	0	579	0	61	39407	25	10010	10	10000	12	10000	50	5706908	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	4	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	0	0	0	640	4	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	314	1	0	0	0	0	0	0	0	1405	39407	69	10010	12	10000	10	10000	50	5708304	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40085	4	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	7468	0	0	640	3	16	3	4	39473	0	10000	10	40085	40181	40085	40038	40038
10024	40037	299	1	0	0	0	0	0	540	0	61	39407	25	10010	10	10018	10	10000	50	5706908	1	40018	0	40180	40037	38130	0	3	38841	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	3	0	0	663	3	16	5	2	39473	0	10000	10	40086	40133	40085	40038	40038
10024	40037	300	1	0	0	0	0	0	9	0	61	39407	25	10016	11	10000	10	10000	50	5708304	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	31452	40084	40037	1	1	10022	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10025	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5708304	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40132	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	3540	0	0	669	2	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40180	317	1	0	0	1	0	1	0	0	94	39407	25	10010	10	10000	10	10147	50	5706908	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40179	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	126	0	0	640	3	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40083

Test 3: Latency 1->2

Code:

  fmla v0.4s, v0.4s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	45	10100	100	10000	100	10000	561	5706908	0	40018	40037	40037	38108	3	38745	10100	206	10000	200	30498	40037	40037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	4	710	1	16	1	1	39479	10000	100	40038	40038	40038	40133	40038
10204	40037	315	1	0	0	0	276	0	61	39396	25	10100	114	10000	100	10296	500	5706908	0	40053	40037	40037	38108	3	38745	10100	200	10000	200	30984	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	4	3635	3	710	1	16	2	1	39479	10000	100	40038	40133	40038	40038	40038
10204	40132	311	0	0	0	0	219	0	61	39407	25	10100	100	10000	100	10000	500	5708304	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	312	0	0	0	0	0	0	201	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	12016	204	10000	200	30999	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	310	0	0	3	0	0	0	2010	39407	25	10100	100	10000	121	10148	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	3	0	710	1	16	1	1	39479	10000	100	40133	40134	40038	40038	40038
10204	40037	311	0	0	0	0	132	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	305	0	0	0	2	12	0	176	39407	25	10100	105	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40084	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40134
10204	40037	300	0	0	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	205	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	1	0	10820	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40085

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	3	4	39475	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	982	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	3	4	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla v0.4s, v1.4s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	61	39389	25	10100	100	10000	100	10147	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	1325	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	6	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10179	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	11	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	747	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	172	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	9	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	104	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	12	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	668	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39511	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10172	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	82	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.4s, v8.4s, v9.s[1]
  movi v1.16b, 0
  fmla v1.4s, v8.4s, v9.s[1]
  movi v2.16b, 0
  fmla v2.4s, v8.4s, v9.s[1]
  movi v3.16b, 0
  fmla v3.4s, v8.4s, v9.s[1]
  movi v4.16b, 0
  fmla v4.4s, v8.4s, v9.s[1]
  movi v5.16b, 0
  fmla v5.4s, v8.4s, v9.s[1]
  movi v6.16b, 0
  fmla v6.4s, v8.4s, v9.s[1]
  movi v7.16b, 0
  fmla v7.4s, v8.4s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	0	0	0	0	0	0	0	515	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10196	4	16	149	0	5	6	20062	21	160000	100	20066	20405	20432	20566	20160
160204	20484	151	0	1	1	6	0	897	528	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	46	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	2	0	2	4	3490	0	0	10115	0	10	16	0	5	6	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	121	80000	118	80000	500	640896	0	20046	20065	20065	20	45	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10120	0	9	16	0	10	5	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	703	0	0	10115	0	10	16	0	10	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10120	0	10	16	0	10	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	63	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10120	0	10	16	0	9	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	84	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	3	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10120	0	5	16	0	11	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	82	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10119	0	10	16	0	10	10	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	444	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10119	0	10	16	0	10	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	10120	0	5	16	0	10	4	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	2	0	0	1	220	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10068	8	5	1	2	41	22	1	1	1	37	37	4	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	0	1	73	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10058	14	5	1	2	43	22	1	1	1	37	35	4	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	1	46	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10070	8	5	1	2	43	22	1	1	1	39	35	5	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	1	777	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10070	8	6	2	2	42	22	1	2	1	37	35	5	20050	2	16	160000	10	20050	20054	20050	20050	20050
160024	20049	150	1	0	0	0	480	25	80012	12	80000	12	80000	62	640000	0	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10073	8	5	1	2	37	22	1	1	1	40	41	4	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	2	0	0	1	819	25	80012	12	80000	12	80000	62	640000	0	1	5	20034	20053	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10074	8	5	1	2	51	22	3	2	2	40	24	4	20050	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	1	815	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10070	8	5	1	2	40	22	1	1	1	29	39	4	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	1	434	25	80012	12	80000	12	80000	62	640000	1	1	5	20034	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10072	8	6	1	2	53	22	1	2	1	42	25	4	20050	2	31	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	135	0	805	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10072	8	6	1	2	36	23	1	1	1	27	38	4	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	1	52	25	80012	12	80000	12	80000	62	640000	1	1	5	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10074	8	5	1	2	23	22	1	1	1	39	43	4	20046	2	16	160000	10	20050	20050	20050	20050	20050

Test 6: throughput

Count: 12

Code:

  fmla v0.4s, v12.4s, v13.s[1]
  fmla v1.4s, v12.4s, v13.s[1]
  fmla v2.4s, v12.4s, v13.s[1]
  fmla v3.4s, v12.4s, v13.s[1]
  fmla v4.4s, v12.4s, v13.s[1]
  fmla v5.4s, v12.4s, v13.s[1]
  fmla v6.4s, v12.4s, v13.s[1]
  fmla v7.4s, v12.4s, v13.s[1]
  fmla v8.4s, v12.4s, v13.s[1]
  fmla v9.4s, v12.4s, v13.s[1]
  fmla v10.4s, v12.4s, v13.s[1]
  fmla v11.4s, v12.4s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	41687	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	5	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5966386	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	41688	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120205	41691	300	0	12	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120202	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	41598	40040	40040	40040	40040
120204	40039	299	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	61	9961	25	120101	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	41691	24932	0	3	26645	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	299	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	41688	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	299	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	0	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	300	0	1	1	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	0	40071	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	41835	41686	1	1	120021	10	9	10	10	120000	10	0	0	6	0	7520	5	0	0	14	16	0	0	0	6	10	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	5	3	1	10	16	0	0	0	9	5	40030	0	0	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	536	40274	46	120010	10	120000	10	120000	50	5630640	0	0	0	40020	41686	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	6	16	0	0	0	8	9	40030	0	0	5	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	0	40020	40039	40039	24955	0	3	25027	120206	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	2	0	7	16	0	0	0	6	10	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	0	40020	40682	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	6	16	0	0	0	9	5	40030	0	0	0	120000	10	40075	41692	41687	40040	40040
120024	41701	300	0	0	0	0	0	0	82	9961	25	120010	10	120000	10	120000	50	5630640	0	1	5	40881	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	6	16	0	0	0	9	10	40030	0	0	0	120000	10	40040	40040	40040	41687	40040
120024	42470	300	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	0	40020	40039	40039	24955	0	3	25019	120208	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	9	16	0	0	0	10	6	40030	0	20	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	1	5	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	6	16	0	0	0	5	9	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	318	0	0	0	0	0	0	61	9961	51	120010	10	120000	10	120000	50	5630640	0	0	5	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	5	0	0	8	16	0	0	0	9	6	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	1	5	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	7520	0	0	0	7	16	0	0	0	9	9	40030	0	0	0	120000	10	40040	40040	40040	40040	40040

FMLA (by element, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations