Firestorm: FMLA (by element, D) measurements

Code:

  fmla d0, d1, v2.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4085
1004	4037	30	0	21	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	48	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	6	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	2	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	6	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	42	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla d0, d1, v2.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	3	710	0	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	4	0	0	710	0	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	4	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	202	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	24	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40086	40086	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	57	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	37	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	570	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	4	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	5	2	0	710	1	3	16	3	4	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	94	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	39473	10000	10	40084	40086	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	103	39407	84	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40228	40037	1	1	10021	10	9	10	10	10000	10	0	2	6	723	2	16	2	2	39592	10000	10	40038	40038	40038	40038	40038
10024	40037	300	42	82	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	3	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	9	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	12	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla d0, d0, v1.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	51	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	315	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	18	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	301	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	3	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla d0, d1, v0.d[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	6	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	93	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10172	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	30	0	441	39407	25	10010	12	10012	10	10000	50	5706908	1	40018	40037	40085	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	5	5	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	5	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	5	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	5	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40071	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	4	9	0	640	6	16	5	6	39896	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	5	6	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	640	6	16	6	5	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	123	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	6	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	4	6	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	5	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla d0, d8, v9.d[1]
  movi v1.16b, 0
  fmla d1, d8, v9.d[1]
  movi v2.16b, 0
  fmla d2, d8, v9.d[1]
  movi v3.16b, 0
  fmla d3, d8, v9.d[1]
  movi v4.16b, 0
  fmla d4, d8, v9.d[1]
  movi v5.16b, 0
  fmla d5, d8, v9.d[1]
  movi v6.16b, 0
  fmla d6, d8, v9.d[1]
  movi v7.16b, 0
  fmla d7, d8, v9.d[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	2	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	705	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80140	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20157	151	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10143	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20076	150	1	0	0	0	0	48	0	722	27	80012	12	80000	12	80000	62	640000	1	1	0	20035	20063	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10050	8	4	1	0	31	27	1	1	1	26	16	20051	2	21	1	160000	10	20055	20055	20055	20055	20055
160024	20054	151	1	0	1	0	0	0	1	230	27	80012	12	80000	12	80000	62	640000	1	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10048	8	5	1	1	26	27	1	1	2	23	26	20051	2	21	1	160000	10	20055	20055	20055	20055	20055
160024	20054	150	1	0	1	0	0	0	1	1055	27	80012	12	80000	12	80000	62	640000	1	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	53	0	3	10049	8	5	1	1	25	27	1	1	1	26	25	20051	2	21	1	160000	10	20055	20055	20055	20055	20055
160024	20054	150	1	0	1	0	0	0	0	104	29	80012	12	80000	12	80000	62	640000	0	1	5	20044	20054	20063	3	23	80012	20	80000	20	240000	20063	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10048	11	8	2	1	29	36	3	2	2	27	26	20051	2	21	1	160000	10	20064	20064	20064	20064	20064
160024	20063	150	1	0	1	0	0	0	0	98	29	80012	12	80000	12	80000	62	640000	1	1	5	20035	20063	20063	3	23	80012	20	80000	20	240000	20063	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10051	11	7	2	1	25	27	3	2	2	18	25	20060	2	41	1	160000	10	20055	20055	20055	20055	20055
160024	20054	150	1	0	1	0	0	0	1	785	27	80012	12	80000	12	80000	62	640000	1	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10046	8	7	2	1	27	36	1	1	1	24	15	20051	2	21	1	160000	10	20055	20055	20055	20055	20055
160024	20063	150	1	0	1	0	0	0	0	104	29	80012	12	80000	12	80000	62	640000	1	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10049	8	7	1	1	26	27	1	1	1	26	48	20051	2	21	2	160000	10	20064	20064	20064	20064	20055
160024	20054	150	1	0	1	0	0	0	1	110	27	80012	12	80000	12	80000	62	640000	1	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10049	8	7	1	1	26	27	1	1	1	17	27	20051	2	41	1	160000	10	20055	20055	20055	20055	20055
160024	20054	150	1	0	1	0	0	0	0	104	27	80012	12	80000	12	80000	62	640000	1	1	5	20044	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10038	8	7	1	1	17	27	1	1	1	25	16	20051	2	21	1	160000	10	20055	20055	20064	20055	20055
160024	20054	150	1	0	1	0	0	0	0	92	27	80012	12	80000	12	80000	62	640000	0	1	5	20035	20054	20054	3	23	80012	20	80000	20	240000	20054	20054	1	1	160021	10	9	10	10	160000	10	0	1	0	0	10049	11	7	2	0	27	36	3	1	2	24	25	20060	2	41	1	160000	10	20055	20055	20055	20055	20055

Test 6: throughput

Count: 12

Code:

  fmla d0, d12, v13.d[1]
  fmla d1, d12, v13.d[1]
  fmla d2, d12, v13.d[1]
  fmla d3, d12, v13.d[1]
  fmla d4, d12, v13.d[1]
  fmla d5, d12, v13.d[1]
  fmla d6, d12, v13.d[1]
  fmla d7, d12, v13.d[1]
  fmla d8, d12, v13.d[1]
  fmla d9, d12, v13.d[1]
  fmla d10, d12, v13.d[1]
  fmla d11, d12, v13.d[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	0	0	413	9961	25	120101	100	120000	100	120000	500	5856942	0	40020	0	41688	40039	26578	3	26649	120100	200	120000	200	360000	41688	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	5	16	1	1	40030	0	120000	100	40040	41689	40040	40040	40040
120204	40039	312	0	0	0	0	409	36348	25	120100	100	120001	100	120000	500	5630640	0	41669	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41689	40040	40040	40040
120204	42470	300	0	0	0	0	168	36348	25	120100	100	120001	100	120000	500	5856942	1	40020	0	41688	40039	24932	3	24997	120100	200	120000	200	360000	40039	41688	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	40040	40040	41689	40040	41689
120204	40039	312	0	0	0	0	654	9961	25	120101	100	120000	100	120000	500	5856942	0	40020	0	41687	40039	26578	3	26646	120100	200	120000	200	360000	41687	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40069	0	120000	100	40040	40040	41688	40040	41688
120204	40039	300	0	0	0	2	529	9961	25	120100	100	120000	100	120000	500	5630640	1	40020	0	40039	41687	24932	3	24997	120100	200	120000	200	360000	40039	41688	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	41682	0	120000	100	40040	41689	40040	40040	40040
120204	40039	312	0	0	0	0	363	9961	25	120101	100	120000	100	120000	500	5860488	1	40020	0	41688	40039	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	41689	40040	40040	41689	40040
120204	41688	300	0	0	0	1	538	9961	25	120101	100	120000	100	120000	500	5860488	1	40020	0	41687	40039	26579	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41689	40040	40040	40040
120204	40090	300	0	33	0	0	1731	9961	25	120100	100	120000	100	120000	500	5630640	1	41669	0	41691	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41689	40040	40040	40040
120204	40039	313	0	0	0	0	517	35689	25	120100	100	120003	100	120000	500	5630640	1	41669	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	41679	0	120000	100	40040	41687	40040	40040	40040
120204	40039	312	0	0	0	0	495	36348	25	120100	100	120001	100	120000	500	5630640	1	41668	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41688	2	1	120201	100	99	100	100	120000	100	0	0	0	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41689	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	41711	316	0	0	0	0	0	0	0	0	0	0	388	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120212	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	19	16	17	16	40030	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	417	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	16	16	18	17	40030	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	424	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360684	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	17	16	16	15	40030	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	1	0	103	9961	25	120013	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	17	16	17	12	40030	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	403	9961	25	120010	10	120001	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	16	16	16	16	40030	1	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	518	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	19	16	18	18	41678	1	120000	10	41097	41670	41030	42002	41156
120024	41306	312	4	1	1	1	9	1	1338	792	5	1	1016	24402	234	120866	13	120788	13	121764	82	5737223	0	0	41960	41000	41919	26162	77	26352	121981	20	122194	20	366003	40890	41471	11	1	120021	10	9	10	10	120000	10	2	2	2	0	4	6978	0	7758	0	0	22	97	21	19	41659	1	120000	10	41797	41336	41267	41250	41755
120024	41823	311	0	1	2	1	11	10	936	880	1	0	1773	23485	250	120866	11	120864	13	121184	50	5767067	0	0	41744	41643	41869	26496	78	26178	121981	20	122010	20	366006	41381	41282	12	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	17	16	18	17	40030	0	120000	10	40040	40040	42471	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	1891	9961	25	120010	10	120000	10	120000	50	5630640	0	0	41667	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	18	16	18	17	40030	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	0	0	0	455	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7520	0	0	17	16	18	18	40030	0	120000	10	40040	40040	40040	40040	40040

FMLA (by element, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations