Firestorm: FMLA (by element, H) measurements

Code:

  fmla h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	42	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3547	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	1	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	32	12	0	189	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	6	1	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	595	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	204	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	7	0	0	0	710	1	3	16	3	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10251	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	44	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	0	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	1338	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1213	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40084	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1210	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1171	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1252	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1353	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1223	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40085	40038	40038
10024	40037	299	0	0	1330	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	9	1246	39407	25	10010	10	10000	10	10000	50	5706908	0	40065	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1288	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla h0, h0, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	1	12	0	82	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	3284	39407	25	10100	100	10000	100	10000	500	5706908	1	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	212	39407	25	10100	100	10000	100	10000	500	5706908	1	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39562	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	168	39407	25	10100	100	10000	100	10000	500	5706908	1	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	804	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40084	1	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	1	170	39407	25	10100	100	10000	100	10000	500	5706908	1	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	710	5	1	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	321	39407	25	10100	100	10000	100	10000	500	5706908	1	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	9	0	149	39407	25	10100	100	10000	100	10000	500	5706908	0	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	1	0	0	0	24	0	214	39407	25	10010	10	10000	10	10000	50	5706908	40123	40037	40084	38169	0	26	38843	10752	20	10642	20	31929	40273	40227	6	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	105	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40084	300	0	0	0	0	0	0	147	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	3639	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	170	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	24885	0	640	3	49	4	4	39619	0	10000	10	40413	40275	40463	40322	40227
10024	40226	304	1	1	7	9	1191	440	7325	39343	145	10055	16	10048	15	10000	50	5706908	40018	40037	40085	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	4	2	1	1	2	3643	4	876	4	96	2	2	40034	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	1461	880	61	39407	25	10017	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	45	38961	11645	20	11782	20	34779	40514	40559	11	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3648	0	640	2	16	2	2	39512	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	8	11	927	968	9615	39353	188	10082	15	10036	20	10888	103	5718076	40403	40368	40357	38166	0	55	38941	11346	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	6	9	1065	968	275	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	1	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40131	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	703	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla h0, h1, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10006	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40080	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	7	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40088	40037	40037	38108	0	3	38763	10100	202	10000	210	30000	40037	40179	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	342	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	339	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	19	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40084	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	42	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	51	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	54	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	30	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	0	2	16	2	2	39473	0	10000	10	40071	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla h0, h8, v9.h[1]
  movi v1.16b, 0
  fmla h1, h8, v9.h[1]
  movi v2.16b, 0
  fmla h2, h8, v9.h[1]
  movi v3.16b, 0
  fmla h3, h8, v9.h[1]
  movi v4.16b, 0
  fmla h4, h8, v9.h[1]
  movi v5.16b, 0
  fmla h5, h8, v9.h[1]
  movi v6.16b, 0
  fmla h6, h8, v9.h[1]
  movi v7.16b, 0
  fmla h7, h8, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	225	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20149	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	40	25	80100	100	80000	100	80000	500	640000	1	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	231	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	183	25	80100	100	80000	100	80000	500	640000	1	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	54	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	1	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20098	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	5	0	0	10030	8	3	1	6	25	2	1	1	6	9	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	2	0	0	10032	8	3	1	9	25	2	1	1	6	9	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10029	8	3	1	10	25	2	1	1	9	6	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	10032	8	3	1	10	25	2	1	1	9	6	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	6	0	0	10032	8	3	1	7	25	2	1	1	7	9	20049	2	40	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	6	0	0	10029	8	4	1	9	25	2	2	2	9	7	20049	2	40	2	160000	10	20053	20062	20053	20062	20053
160024	20061	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	0	1	5	20033	20052	20061	0	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	50	135	0	10032	11	3	1	6	25	2	1	1	9	7	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20042	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10032	8	3	1	6	25	2	1	1	7	9	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	20	168	0	10030	8	3	1	9	25	2	1	1	6	9	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	18	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	7	0	0	10029	8	4	1	9	25	2	1	1	7	9	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 12

Code:

  fmla h0, h12, v13.h[1]
  fmla h1, h12, v13.h[1]
  fmla h2, h12, v13.h[1]
  fmla h3, h12, v13.h[1]
  fmla h4, h12, v13.h[1]
  fmla h5, h12, v13.h[1]
  fmla h6, h12, v13.h[1]
  fmla h7, h12, v13.h[1]
  fmla h8, h12, v13.h[1]
  fmla h9, h12, v13.h[1]
  fmla h10, h12, v13.h[1]
  fmla h11, h12, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	3	61	9961	25	120100	100	120000	100	120000	500	5851993	1	40020	40039	41686	26577	25	26649	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	41677	0	120000	100	40040	40040	40040	41692	40040
120204	40039	312	0	0	0	61	40274	25	120100	100	120000	100	120000	500	5851993	0	41667	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	40030	0	120000	100	40040	41692	41692	40040	41687
120204	40039	312	0	0	3	61	9961	25	120100	100	120000	100	120000	500	5851993	0	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	41677	0	120000	100	41692	41692	42471	40040	41687
120204	41686	300	0	0	0	61	35689	25	120100	100	120000	100	120000	500	5851993	0	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	41677	0	120000	100	40040	40040	41687	40040	41692
120204	41686	299	0	0	3	61	37966	25	120100	100	120000	100	120000	500	5851869	0	41667	40039	41686	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	40030	0	120000	100	40040	40040	41692	40040	40040
120204	40039	310	0	0	0	159	9938	25	120200	116	120000	100	120000	500	5630640	1	41667	41686	40039	24932	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	41677	0	120000	100	40040	40040	40040	41687	40040
120204	41686	300	0	0	3	61	9961	25	120100	100	120000	100	120000	500	5630640	1	40020	40039	41691	26577	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	6	7610	1	16	1	1	40030	0	120000	100	40040	40040	40040	41687	40040
120204	41686	300	0	0	3	61	9961	25	120103	100	120003	100	120000	500	5630640	0	40020	40039	41686	26582	3	26649	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	40030	0	120000	100	40040	40040	41692	40040	41692
120204	41691	300	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5851993	0	40020	40039	41688	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	2	7610	1	16	1	1	40030	0	120000	100	40040	41692	41687	40040	40040
120204	40039	312	0	0	0	61	35689	25	120103	100	120001	100	120196	500	5630640	0	40020	40039	41686	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	1	16	1	1	41677	0	120000	100	40040	40040	40040	41712	41692

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	42470	318	0	0	0	0	0	0	0	90	37966	25	120010	10	120000	10	120000	50	5630640	1	1	41672	41691	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	1	3	0	0	0	7522	3	2	1	14	16	2	1	1	3	9	41678	0	15	9	4	120000	10	40040	40040	40040	41710	40040
120024	40039	300	0	0	0	0	12	0	1	67	9961	25	120011	10	120000	10	120000	50	5630640	1	0	41672	40039	40039	24955	3	26667	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	1	0	0	0	0	7522	3	1	1	3	16	2	1	1	5	3	40030	0	30	9	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	1	0	0	36	0	0	67	35689	25	120010	10	120000	10	120000	50	5851993	1	1	41667	40039	40039	24955	3	25019	120010	20	120000	20	360000	41691	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	3	16	2	1	2	5	3	40030	0	15	17	4	120000	10	40040	41688	40040	41692	40040
120024	40039	312	0	0	0	0	0	0	0	67	9961	25	120013	10	120000	10	120000	50	5630640	1	1	40020	40039	41686	24955	3	25019	120010	20	120000	20	360000	40039	42470	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	5	16	2	1	1	5	3	40030	0	15	9	4	120000	10	40040	40040	40040	40040	41687
120024	40039	300	0	0	0	0	0	0	0	67	37966	25	120013	10	120001	10	120000	50	5630640	1	1	40020	40039	41686	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120022	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	5	16	2	1	1	3	5	40030	0	15	9	4	120000	10	41687	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	1	0	7522	3	1	1	5	16	2	1	1	5	3	40030	0	15	9	4	120000	10	40040	40040	40040	41639	40040
120024	40039	300	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	41686	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	5	5	40030	0	15	9	4	120000	10	40040	40040	41692	40040	40040
120024	40039	299	0	0	0	0	0	0	0	447	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	5	16	2	1	1	3	9	40030	0	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	11	16	2	1	1	4	5	40030	0	15	9	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	0	40020	40039	41687	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	1	7522	3	1	1	4	16	2	1	1	9	4	40030	0	15	9	4	120000	10	41689	40040	40040	40040	40040

FMLA (by element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations