Firestorm: FMLA (vector, 4H) measurements

Code:

  fmla v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	2	24	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3533	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	186	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	4	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5708304	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40083	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	710	0	2	16	3	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	45	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	3	39479	0	10000	100	40038	40086	40038	40038	40038
10204	40037	300	0	1	0	0	0	0	0	441	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	141	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	0	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38757	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	710	0	2	16	2	2	39479	0	10000	100	40087	40038	40086	40038	40038
10204	40037	300	0	1	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	204	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	2	0	710	0	2	16	2	2	39479	0	10000	100	40038	40086	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	1061	39407	25	10100	100	10000	100	10000	522	5706908	0	40018	40037	40037	38108	3	38745	10252	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	557	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38112	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	710	0	2	26	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	102	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	42	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	6	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	14329	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	1	39	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	15	103	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	27	1023	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	294	61	39407	25	10010	10	10000	10	10000	50	5708304	0	40018	40037	40037	38130	12	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	27	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	640	2	24	2	2	39473	10000	10	40038	40038	40086	40038	40038
10024	40037	299	1	0	18	61	39407	25	10010	10	10000	10	10000	50	5708304	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	231	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla v0.4h, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	d8	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	0	132	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	17	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	114	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	105	0	82	39398	25	10100	100	10000	100	10000	500	5706908	0	40018	40084	40037	38108	3	38745	10100	200	10000	200	30000	40037	40085	1	1	10201	100	99	100	100	10000	100	0	2	0	0	5	0	0	710	1	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	27	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	204	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	1	1	21	0	1227	39389	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	279	0	3851	39398	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	3	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	183	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	291	0	61	39398	25	10100	100	10000	100	10148	500	5706908	0	40018	40086	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	1	3368	4	710	2	16	0	2	2	39479	10000	100	40086	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	258	0	61	39407	44	10100	114	10000	100	10148	500	5706908	0	40053	40085	40037	38108	3	38764	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	0	1	0	0	2	732	2	16	0	2	2	39479	10000	100	40038	40038	40085	40038	40038
10204	40084	300	0	0	1	1	0	27	0	61	39407	45	10100	119	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	710	2	16	0	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	3	0	0	126	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5709700	1	40053	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	55	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38135	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40177	38130	3	38767	10010	20	10000	20	30000	40037	40076	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla v0.4h, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	2	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	916	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	4	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	4	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40084	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10205	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	127	39407	25	10100	100	10000	100	10000	500	5706908	0	4	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40158	40085	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	251	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	3	10000	10	40321	40417	40465	40417	40420
10024	40467	303	0	1	1	9	8	1200	792	0	7388	39335	180	10067	20	10048	12	11332	55	5718918	0	40298	40500	40416	38168	42	38915	11199	24	11451	24	33723	40462	40368	7	1	10021	10	9	10	10	10000	10	2	2	0	2	4	28758	0	809	3	104	4	3	39795	5	10000	10	40229	40416	40463	40464	40462
10024	40463	303	1	0	1	10	8	1068	792	1	4157	39326	101	10062	16	10054	16	11184	70	5719472	0	40333	40467	40461	38166	23	38938	11345	22	10808	26	34371	40453	40415	11	1	10021	10	9	10	10	10000	10	2	0	2	1	4	20788	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	411	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.4h, v8.4h, v9.4h
  movi v1.16b, 0
  fmla v1.4h, v8.4h, v9.4h
  movi v2.16b, 0
  fmla v2.4h, v8.4h, v9.4h
  movi v3.16b, 0
  fmla v3.4h, v8.4h, v9.4h
  movi v4.16b, 0
  fmla v4.4h, v8.4h, v9.4h
  movi v5.16b, 0
  fmla v5.4h, v8.4h, v9.4h
  movi v6.16b, 0
  fmla v6.4h, v8.4h, v9.4h
  movi v7.16b, 0
  fmla v7.4h, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	151	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	3	10111	1	16	1	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	6	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	230	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	24	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	3	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	3	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160202	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2526

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20085	151	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10033	8	1	1	25	25	2	1	1	16	15	20049	2	20	1	160000	10	20062	20053	20062	20053	20053
160024	20061	150	0	303	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10031	8	5	1	20	25	2	1	2	19	11	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	396	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20033	20061	20061	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10034	8	5	1	12	25	2	1	1	17	11	20049	2	40	1	160000	10	20053	20053	20053	20053	20053
160024	20061	150	0	6	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10038	8	5	1	20	25	2	1	1	10	15	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20042	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10038	8	5	1	22	25	2	1	1	20	19	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20061	150	0	0	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10038	8	5	1	9	25	2	1	1	15	10	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	294	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10038	8	5	1	15	25	2	1	1	15	15	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	46	27	80012	12	80000	12	80000	62	640000	2	1	5	20042	20061	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10033	8	5	1	10	25	2	1	1	14	11	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	52	29	80012	12	80000	12	80000	62	640000	2	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10033	8	5	1	20	25	2	1	1	13	15	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	90	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10038	8	5	1	14	25	2	1	1	15	15	20049	2	20	1	160000	10	20053	20053	20053	20146	20053

Test 6: throughput

Count: 16

Code:

  fmla v0.4h, v16.4h, v17.4h
  fmla v1.4h, v16.4h, v17.4h
  fmla v2.4h, v16.4h, v17.4h
  fmla v3.4h, v16.4h, v17.4h
  fmla v4.4h, v16.4h, v17.4h
  fmla v5.4h, v16.4h, v17.4h
  fmla v6.4h, v16.4h, v17.4h
  fmla v7.4h, v16.4h, v17.4h
  fmla v8.4h, v16.4h, v17.4h
  fmla v9.4h, v16.4h, v17.4h
  fmla v10.4h, v16.4h, v17.4h
  fmla v11.4h, v16.4h, v17.4h
  fmla v12.4h, v16.4h, v17.4h
  fmla v13.4h, v16.4h, v17.4h
  fmla v14.4h, v16.4h, v17.4h
  fmla v15.4h, v16.4h, v17.4h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40145	307	0	0	0	0	0	61	0	25	160122	100	160000	100	160000	500	1280000	40021	40040	40043	19973	0	3	21185	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	3	16	1	1	40037	0	160000	100	40041	40041	40041	40041	40041
160204	41205	308	0	0	84	0	0	61	0	25	160100	100	160022	100	160000	500	1280000	42316	40040	40040	21095	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	40041	41191	41206	40041	40041
160204	40040	300	0	0	0	0	22	42	4541	25	160100	100	160000	100	160000	500	1280000	40021	40040	40040	19973	0	3	19999	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	41191	40044	40041	40041	40041
160204	40040	300	0	0	0	0	0	42	4541	25	160122	100	160000	100	160000	500	1280000	41171	40040	40040	21111	0	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	41191	40044	40041	40041	40041
160204	40040	299	0	0	0	0	22	42	4485	25	160100	100	160001	100	160000	500	5715261	40021	40040	41190	21095	0	3	19998	160100	200	160000	200	480000	41190	41205	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	41191	40044	40041	40041	40041
160204	40040	300	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	40021	40040	40040	19973	0	3	21163	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	40041	41191	41206	40041	41206
160204	40040	299	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	40021	40040	41190	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	41202	0	160000	100	40041	40041	41191	41206	40041
160204	40040	300	0	0	0	0	0	42	4485	25	160100	100	160022	100	160000	500	1280000	40021	40043	41190	21095	0	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	40041	41191	40044	40041	40041
160204	40040	299	0	0	0	0	0	707	0	25	160122	100	160000	100	160000	500	5705774	40021	40040	41190	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	0	10110	1	16	1	1	41202	0	160000	100	40041	40041	40041	40041	40041
160204	40040	300	0	0	0	0	0	42	0	25	160100	100	160022	100	160000	500	1319999	40021	40040	40040	21095	0	3	19998	160100	200	160000	200	480000	41205	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	0	160000	100	40041	40041	41191	42286	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2547

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40758	300	0	0	0	0	80	47	8955	25	160010	10	160000	10	160000	50	5868895	1	1	42308	42327	40040	19996	0	3	22307	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	10	20	40037	15	7	160000	10	42319	40041	42319	42328	42319
160024	40040	317	0	0	0	0	0	73	0	25	160090	10	160000	10	160000	50	1280000	0	1	42308	40040	42327	22237	0	3	20020	160010	20	160000	20	480000	42327	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	19	16	2	2	2	20	20	42324	30	7	160000	10	40041	42328	40041	42328	40041
160024	40040	317	0	0	0	0	80	67	8955	25	160090	10	160080	10	160000	50	5868895	1	1	42308	42296	42327	22237	0	3	22307	160010	20	160000	20	480000	42327	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	0	0	10022	3	1	1	19	16	2	1	1	9	19	42324	15	7	160000	10	40041	42286	40041	42328	42328
160024	42327	300	0	0	0	0	80	110	8955	25	160010	10	160000	10	160000	50	5868895	1	1	40021	42327	42327	19996	33	3	20020	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	19	16	2	1	1	20	20	40037	15	7	160000	10	40041	42328	40041	42328	42328
160024	42327	299	0	0	0	0	0	712	0	25	160090	10	160080	10	160000	50	1280000	1	1	42308	40040	42327	22237	33	3	22307	160010	20	160000	20	480000	42327	40040	1	1	160022	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	2	19	16	2	1	1	20	20	42324	15	5	160000	10	42328	40041	42328	40041	40041
160024	40040	317	0	0	0	0	0	67	8955	25	160090	10	160043	10	160000	50	5868895	1	1	40021	42327	42327	22237	33	3	20020	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	6	1	1	19	16	2	2	1	7	19	40037	30	7	160000	10	40041	42328	42328	42328	42328
160024	40040	317	0	0	0	0	0	67	8955	25	160010	10	160080	10	160000	50	1280000	1	1	40021	40040	42327	19996	0	3	22307	160010	20	160000	20	480000	42327	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	3	1	1	19	16	2	1	1	16	19	40037	15	5	160000	10	40041	40041	42286	40041	42319
160024	40040	317	0	0	0	0	80	67	8955	25	160090	10	160080	10	160000	50	1280000	0	1	40021	42327	42327	19996	0	3	22307	160010	20	160000	20	480000	42327	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	6	1	2	19	16	2	1	1	20	20	42324	15	7	160000	10	41230	42328	42328	42328	42315
160024	42327	317	0	0	0	0	80	73	0	25	160010	10	160000	10	160000	50	5868895	1	1	40021	42327	42327	22237	33	3	22307	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	1	1	19	16	2	1	1	19	7	40037	15	5	160000	10	40041	42328	40041	42328	40041
160024	40040	317	0	0	0	0	0	47	0	25	160090	10	160080	10	160000	50	1280000	0	1	42308	42327	40040	22237	0	3	20020	160010	20	160000	20	480000	42327	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	19	16	2	19	1	20	7	40037	30	7	160000	10	40041	42328	40041	42328	42328

FMLA (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations