Firestorm: FMLA (vector, 4S) measurements

Code:

  fmla v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	209	3407	25	1000	1000	1000	531908	1	4018	4037	4083	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	108	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	2	2	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	19	10000	100	40038	40038	40038	40038	40038
10204	40181	300	0	0	0	0	0	61	39407	44	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	3	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	18	1	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	3	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10147	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	2	2	39480	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	536	5707315	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	739	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	124	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	1398	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10157	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	260	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39513	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40086	40085	40038	40038
10204	40037	299	0	1	1	0	0	208	39407	25	10100	100	10000	100	10000	500	5708689	0	40018	40084	40132	38108	3	38745	10100	200	10327	206	30483	40134	40132	3	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	522	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	285	176	124	39407	25	10010	10	10000	10	10000	50	5706908	0	40053	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40226	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	27	0	61	39407	25	10010	10	10000	10	10000	50	5712492	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	6	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40133	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	3	0	0	640	2	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	2	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5708304	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	24	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	124	39407	25	10010	12	10000	10	10148	50	5706908	0	40018	40084	40037	38135	3	38786	10010	20	10000	20	30483	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40227

Test 4: Latency 1->3

Code:

  fmla v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38115	7	38741	10100	204	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	710	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40081	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	577	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	18	3	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	105	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	2866	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38789	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	27	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40113	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	145	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	631	39407	44	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  fmla v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  fmla v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  fmla v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  fmla v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  fmla v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  fmla v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  fmla v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10116	4	16	4	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10116	3	16	4	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	3	16	2	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	3	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	10116	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10116	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	61	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10112	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	63	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	2	0	10116	3	16	3	3	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20076	150	0	0	0	0	0	24	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10036	3	2	2	32	34	4	2	2	12	20	20058	2	40	2	160000	10	20062	20062	20062	20062	20062
160024	20061	151	0	0	0	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	1	5	20033	20061	20052	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10043	8	4	1	13	25	2	1	1	17	19	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	1	5	20033	20135	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10034	8	4	1	11	25	2	1	1	13	11	20116	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	1	0	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	1	3	10040	8	5	2	11	34	4	2	2	10	16	20137	2	40	2	160000	10	20062	20062	20062	20062	20062
160024	20086	151	0	1	1	1	1	36	88	52	29	80012	12	80000	12	80000	62	640000	0	1	5	20042	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10041	8	5	1	11	34	4	2	2	11	14	20049	2	40	1	160000	10	20062	20062	20053	20053	20062
160024	20061	150	0	0	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20061	20052	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10039	11	5	2	13	34	4	2	2	12	19	20058	2	40	2	160000	10	20062	20062	20062	20062	20062
160024	20061	150	0	0	0	0	0	0	0	616	27	80012	12	80000	12	80000	62	640000	0	1	5	20033	20061	20061	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10036	8	5	2	13	34	4	2	2	13	13	20049	2	40	1	160000	10	20062	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	18	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20061	20052	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10040	8	6	2	17	34	4	2	1	13	11	20058	2	40	2	160000	10	20062	20062	20062	20062	20062
160024	20061	150	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10036	8	5	1	14	25	2	1	1	14	11	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	27	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20061	1	1	160021	10	9	10	10	160000	10	0	0	10039	11	6	2	14	25	4	2	2	14	11	20058	2	40	2	160000	10	20062	20062	20062	20062	20062

Test 6: throughput

Count: 16

Code:

  fmla v0.4s, v16.4s, v17.4s
  fmla v1.4s, v16.4s, v17.4s
  fmla v2.4s, v16.4s, v17.4s
  fmla v3.4s, v16.4s, v17.4s
  fmla v4.4s, v16.4s, v17.4s
  fmla v5.4s, v16.4s, v17.4s
  fmla v6.4s, v16.4s, v17.4s
  fmla v7.4s, v16.4s, v17.4s
  fmla v8.4s, v16.4s, v17.4s
  fmla v9.4s, v16.4s, v17.4s
  fmla v10.4s, v16.4s, v17.4s
  fmla v11.4s, v16.4s, v17.4s
  fmla v12.4s, v16.4s, v17.4s
  fmla v13.4s, v16.4s, v17.4s
  fmla v14.4s, v16.4s, v17.4s
  fmla v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	41076	300	2	0	17	31	0	25	160143	100	160064	100	160019	500	5705933	0	40021	41190	42285	21169	6	19991	160119	200	160024	200	480072	42285	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	1	16	0	0	40037	160000	100	42286	40041	41191	41206	41191
160204	40040	309	0	0	43	31	4486	25	160108	100	160080	100	160019	500	5715386	0	40021	40040	40040	21115	6	19991	160123	200	160024	200	480072	41205	40040	1	1	160201	100	99	100	100	160000	100	6	0	0	1	1	1	10118	0	16	0	0	41206	160000	100	41206	40041	41191	41206	42286
160204	40040	308	0	24	22	61	4541	25	160100	100	160001	100	160000	500	1280000	0	40021	40040	40040	21111	3	21163	160100	200	160000	200	480000	40043	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	41187	160000	100	40041	41191	41206	41191	41206
160204	41205	300	0	0	0	61	4485	25	160122	100	160022	100	160000	500	1319999	0	42266	40040	40040	19973	3	21163	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	41187	160000	100	40041	40041	40041	40041	41206
160204	40040	300	0	0	43	42	0	25	160100	100	160000	100	160000	500	5715261	0	41185	41190	41205	19973	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	40041	41191	41206
160204	41205	309	0	0	43	61	4485	25	160122	100	160022	100	160000	500	5705774	0	40021	40040	40040	21095	3	19998	160100	200	160000	200	480000	41190	41205	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	41202	160000	100	40041	40041	41191	42286	40041
160204	41190	317	0	0	17	61	0	25	160143	100	160000	100	160000	500	1280000	0	41171	40040	40040	19973	3	21148	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	3	0	0	0	0	10110	1	16	2	1	40037	160000	100	42286	40041	40041	40041	40041
160204	40040	300	0	0	0	42	0	25	160100	100	160017	100	160000	500	5705774	0	41171	40040	40040	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	41191	41206	40041
160204	40040	300	0	0	0	42	0	52	160100	100	160017	100	160000	500	5715261	0	40021	40043	40040	19973	3	21148	160100	200	160000	200	480000	41190	41209	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	41206	41191	40042	40041	40041
160204	40040	300	0	27	0	61	0	25	160100	100	160000	100	160000	500	1280000	0	41186	41209	40040	21111	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	40041	41191	41206	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40062	300	0	0	0	0	0	0	0	0	0	0	67	4589	25	160010	10	160051	10	160000	50	5728047	1	1	0	40021	40040	40040	19996	0	3	21206	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	81	10026	11	2	1	0	7	16	4	1	1	3	4	3	40037	0	40	27	160000	10	42319	40041	40041	40041	40041
160024	41226	308	0	0	0	0	0	0	0	0	0	17	54	0	25	160011	10	160000	10	160000	50	5728047	1	1	5	41207	41226	41226	21141	0	3	21206	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	11	3	1	0	4	16	2	1	1	3	3	3	42315	0	20	8	160000	10	40041	42319	40041	40043	40041
160024	40040	300	0	0	0	0	0	0	0	0	0	1	67	0	25	160070	10	160002	10	160000	50	1280000	1	1	5	42262	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	10026	11	4	1	0	3	16	2	1	1	4	3	3	41202	0	20	7	160000	10	41227	41227	41227	41227	41227
160024	42285	300	0	0	0	0	0	0	0	0	0	60	47	0	25	160070	10	160001	10	160000	50	5868333	1	1	5	41200	42318	40040	19996	0	3	22261	160010	20	160000	20	480000	40041	41219	1	1	160021	10	9	10	10	160000	10	0	0	0	0	102	10026	11	4	1	0	3	16	2	1	1	6	8	3	40040	0	20	7	160000	10	40041	40041	40043	40041	40041
160024	40040	317	0	0	0	0	0	0	0	0	0	60	68	0	25	160010	10	160001	10	160000	50	1280000	1	1	5	41207	40040	41226	19996	0	3	21199	160010	20	160000	20	480000	41205	41219	1	1	160021	10	9	10	10	160000	10	0	0	0	0	120	10026	11	5	1	0	4	16	2	1	1	4	4	3	41202	0	20	8	160000	10	40041	42319	40041	40044	41220
160024	40040	316	0	1	0	0	0	0	0	0	0	0	732	4576	44	160070	10	160017	10	160000	50	5728047	1	1	5	41200	40040	41226	19996	0	3	20020	160010	20	160000	20	480000	40042	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	18	10026	11	5	1	0	3	16	2	1	1	4	4	3	42315	0	20	7	160000	10	41227	41227	41227	41227	41206
160024	40040	317	0	0	0	0	0	0	0	0	0	0	67	0	25	160028	10	160000	10	160000	50	5868333	1	1	5	42299	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	41226	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	126	10025	11	5	1	0	3	16	2	1	1	4	4	3	40037	0	20	8	160000	10	40041	42319	40041	42319	40041
160024	40040	300	0	0	0	0	0	0	0	0	0	0	48	0	25	160028	10	160000	10	160000	50	1280000	1	1	5	42299	40040	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	1	87	10025	11	5	1	0	5	16	2	4	1	5	5	3	41216	0	20	8	160000	10	40041	40043	42302	40041	40041
160024	40040	299	0	0	0	1	0	0	0	0	0	0	49	8970	25	160063	10	160001	10	160000	50	5868333	1	1	5	40023	40040	42318	19996	0	3	20020	160010	20	160000	20	480000	42318	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	183	10026	11	5	1	0	3	16	2	1	1	4	2	3	42315	0	20	8	160000	10	40041	42319	40041	40043	40041
160024	40040	317	0	0	0	0	0	0	0	0	0	0	67	8844	25	160028	10	160000	10	160000	50	5710654	1	1	5	40021	40040	41226	19996	0	3	21206	160010	20	160000	20	480000	42302	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	0	87	10026	11	5	1	0	5	16	2	1	1	5	5	3	42315	0	20	8	160000	10	40043	40042	40041	40041	40041

FMLA (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations