Firestorm: FMLA (vector, 8H) measurements

Code:

  fmla v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	198	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	3	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	9	38745	10100	204	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	3	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	536	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	3	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40085	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	3	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	1	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	3	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40085	40038	40038	40038
10024	40037	317	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	668	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10161	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40084	300	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	787	1	16	1	1	39479	0	10000	100	40038	40038	40038	40085	40038
10204	40037	299	0	0	162	176	61	39389	63	10133	129	10006	123	10148	500	5706908	40088	40130	40084	38108	3	38745	10100	204	10332	202	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	2	0	0	2	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5705468	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10166	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	7185	0	0	710	2	16	1	1	39479	14	10000	100	40038	40038	40134	40085	40038
10204	40085	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	12	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30483	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	2	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	4	540	352	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10058	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	310	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38786	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	346	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	283	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	43	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	6	16	3	3	39545	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40076	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.8h, v8.8h, v9.8h
  movi v1.16b, 0
  fmla v1.8h, v8.8h, v9.8h
  movi v2.16b, 0
  fmla v2.8h, v8.8h, v9.8h
  movi v3.16b, 0
  fmla v3.8h, v8.8h, v9.8h
  movi v4.16b, 0
  fmla v4.8h, v8.8h, v9.8h
  movi v5.16b, 0
  fmla v5.8h, v8.8h, v9.8h
  movi v6.16b, 0
  fmla v6.8h, v8.8h, v9.8h
  movi v7.16b, 0
  fmla v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	27	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	3	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	48	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	3	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	3	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20135	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	3704	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	100	80140	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10114	4	16	4	4	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20070	150	0	0	46	25	80012	12	80000	12	80000	62	640000	1	0	0	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10026	13	5	1	6	20	2	1	1	3	4	20044	2	15	0	160000	10	20069	20056	20052	20048	20048
160024	20047	150	0	0	52	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10026	13	7	1	3	20	2	1	1	4	4	20044	2	15	0	160000	10	20069	20052	20052	20048	20048
160024	20047	150	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10027	13	8	2	4	24	2	1	2	4	3	20044	2	15	0	160000	10	20056	20048	20048	20048	20048
160024	20047	150	0	0	46	25	80012	12	80000	12	80000	62	640000	0	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	7	129	10027	13	5	1	4	20	2	1	2	4	4	20044	2	15	0	160000	10	20068	20048	20048	20048	20048
160024	20047	150	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20051	20047	1	1	160021	10	9	10	10	160000	10	0	0	10027	13	6	1	3	20	2	1	1	4	4	20044	2	15	0	160000	10	20060	20052	20048	20048	20052
160024	20047	156	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	9	0	10026	13	6	1	3	20	2	1	1	4	4	20044	2	15	0	160000	10	20056	20052	20048	20048	20048
160024	20051	150	0	0	52	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	6	0	10026	16	6	1	4	24	2	1	1	4	4	20048	2	30	0	160000	10	20068	20048	20048	20048	20048
160024	20047	150	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80109	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10027	13	6	1	4	20	2	1	1	4	3	20044	2	15	0	160000	10	20060	20048	20048	20048	20130
160024	20047	151	1	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10026	13	6	1	4	20	2	1	1	3	4	20044	2	15	0	160000	10	20056	20048	20048	20048	20048
160024	20047	150	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	10	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	10026	13	6	1	4	24	2	1	1	3	4	20044	2	15	0	160000	10	20056	20048	20048	20048	20048

Test 6: throughput

Count: 16

Code:

  fmla v0.8h, v16.8h, v17.8h
  fmla v1.8h, v16.8h, v17.8h
  fmla v2.8h, v16.8h, v17.8h
  fmla v3.8h, v16.8h, v17.8h
  fmla v4.8h, v16.8h, v17.8h
  fmla v5.8h, v16.8h, v17.8h
  fmla v6.8h, v16.8h, v17.8h
  fmla v7.8h, v16.8h, v17.8h
  fmla v8.8h, v16.8h, v17.8h
  fmla v9.8h, v16.8h, v17.8h
  fmla v10.8h, v16.8h, v17.8h
  fmla v11.8h, v16.8h, v17.8h
  fmla v12.8h, v16.8h, v17.8h
  fmla v13.8h, v16.8h, v17.8h
  fmla v14.8h, v16.8h, v17.8h
  fmla v15.8h, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40149	303	0	0	60	42	0	25	160100	100	160060	100	160000	500	5717939	0	40021	40040	41227	19973	3	21188	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	2	0	0	0	10110	2	16	2	1	40037	160000	100	40041	40041	40041	41228	40041
160204	40040	309	0	0	0	42	0	25	160100	100	160035	100	160000	500	1280000	0	40021	41227	40040	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	1	0	0	0	10110	3	16	1	2	40037	160000	100	40041	41228	40041	40041	40041
160204	40040	300	0	0	54	42	0	25	160160	100	160000	100	160000	500	1280000	1	40021	40040	41227	19973	3	19998	160100	200	160000	200	480000	41227	40040	1	1	160201	100	99	100	100	160000	100	2	0	3	0	10110	3	16	2	1	41224	160000	100	40041	40041	41228	40041	41228
160204	40040	300	0	176	0	42	0	60	160100	101	160037	100	160106	500	1280000	1	40021	40040	41227	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	1	0	0	0	10110	2	16	2	1	40037	160000	100	40041	41228	40041	40041	40041
160204	40040	308	0	0	0	102	4614	25	160100	100	160060	100	160000	500	1280000	0	40021	42317	41227	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	3	0	0	0	10110	1	16	1	1	41224	160000	100	42336	40041	41228	40041	41228
160204	41227	300	0	0	0	42	0	25	160160	100	160000	100	160000	500	5717939	0	40021	41227	40040	21132	3	19998	160100	200	160000	200	480000	40040	41227	1	1	160201	100	99	100	100	160000	100	1	0	0	0	10110	2	16	1	1	40037	160000	100	40041	40041	41228	40041	41228
160204	40040	300	0	0	0	42	0	25	160100	100	160000	100	160000	500	5717939	0	41208	40040	40040	21132	3	22275	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	1	0	0	0	10110	1	16	2	2	40037	160000	100	40041	41228	40041	40041	40041
160204	40040	300	0	0	0	61	0	25	160100	100	160060	100	160000	500	1280000	1	40021	41227	40040	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	4	0	0	0	10110	1	16	1	2	40037	160000	100	40041	40041	40041	40041	41228
160204	40040	300	0	0	0	517	0	25	160100	100	160000	100	160000	500	5717939	1	41208	40040	41227	19973	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	3	2	42314	160000	100	40041	41220	41205	41228	40041
160204	40040	309	9	0	0	61	0	25	160160	100	160000	100	160000	500	5717939	0	40021	40040	41227	19973	3	21185	160100	200	160000	200	480000	41227	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	41228	40041	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2577

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40426	300	0	0	60	26	399	4614	25	160010	10	160060	10	160000	50	5717939	1	1	40021	41227	40040	21154	3	21207	160010	20	160000	20	480000	40043	41227	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	2	2	21	16	4	2	2	8	19	41224	0	30	10	160000	10	41228	40041	40041	40041	40041
160024	41227	300	0	0	60	21	141	4614	25	160070	10	160060	10	160000	50	5717939	0	1	41200	41227	41227	19996	3	21207	160010	20	160000	20	480000	40040	40043	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	1	1	19	9	41224	0	15	5	160000	10	40041	41228	40041	40041	40041
160024	40040	309	0	0	0	20	109	4614	25	160070	10	160060	10	160000	50	5717939	1	1	40021	41227	41227	21154	3	21207	160010	20	160000	20	480000	41227	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	1	1	10	20	41224	0	15	7	160000	10	41228	40041	40041	41228	41228
160024	40040	300	0	0	60	20	88	4614	25	160070	10	160000	10	160000	50	5717939	1	1	40021	41227	40040	21154	3	21185	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	1	1	19	7	41224	0	15	5	160000	10	41228	41228	41228	41228	41228
160024	41227	308	0	0	60	20	68	0	25	160010	10	160060	10	160000	50	1280000	1	1	40021	41227	41227	19996	3	21207	160010	20	160000	20	480000	40040	41227	1	1	160021	10	9	10	10	160000	10	0	9	0	10024	3	1	1	19	16	2	1	1	20	19	40037	1	15	7	160000	10	40041	41228	41228	40041	41228
160024	40040	300	0	0	60	23	88	0	25	160010	10	160060	10	160000	50	1280000	1	1	40021	40040	40040	21154	3	20020	160010	20	160000	20	480000	40040	41227	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	1	1	19	19	41224	0	15	5	160000	10	41228	41228	40041	40041	40041
160024	41227	309	0	0	0	22	70	4614	25	160070	10	160060	10	160000	50	5717939	1	1	41208	41227	41227	21154	3	20020	160010	20	160000	20	480000	41227	41227	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	1	1	16	19	41224	0	15	7	160000	10	41228	41228	42318	40044	41228
160024	41227	309	0	0	60	22	90	4614	25	160070	10	160060	10	160000	50	5717939	1	1	40021	40040	40040	21154	3	20020	160010	20	160000	20	480000	41227	40091	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	19	16	2	2	1	19	19	40040	0	15	7	160000	10	41228	41228	40041	40041	41228
160024	41227	308	0	0	60	22	557	0	25	160011	10	160000	10	160000	50	5717939	1	1	41208	40040	41227	21154	3	21122	160010	20	160000	20	480000	41227	41227	1	1	160021	10	9	10	10	160000	10	0	0	0	10024	3	1	1	19	16	4	1	1	19	19	41224	0	15	5	160000	10	41228	41228	42318	41228	41228
160024	41227	309	0	0	60	24	176	4614	25	160010	10	160060	10	160000	50	1280000	1	1	41208	41227	41227	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	1	10022	3	1	1	9	16	2	1	1	19	9	40037	0	15	7	160000	10	40041	41228	41228	41228	41228

FMLA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations