Firestorm: FMLSL2 (vector, 2S) measurements

Code:

  fmlsl2 v0.2s, v1.2h, v2.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	0	0	0	0	0	314	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4084	1	1	1001	1000	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3914	1000	1160	3054	4073	4133	2	1	1001	1000	2	2	1	0	3565	0	94	1	37	1	1	3509	1000	4086	4085	4085	4038	4086
1004	4074	30	1	0	1	1	0	0	0	327	3398	49	1000	1000	1148	533304	1	4053	4084	4073	3258	8	3907	1139	1000	3486	4085	4085	2	1	1001	1000	0	2	0	2	2193	0	73	1	24	1	1	3489	1000	4086	4074	4085	4074	4074
1004	4084	30	0	0	1	1	144	88	0	958	3398	49	1000	1006	1000	533304	1	4018	4084	4037	3262	7	3915	1148	1160	3483	4084	4073	2	1	1001	1000	0	2	2	0	3550	2	94	1	40	1	1	3473	1000	4084	4038	4086	4086	4084
1004	4084	30	0	1	1	1	135	88	1	873	3398	45	1006	1000	1082	531908	1	4053	4073	4085	3261	8	3914	1148	1163	3483	4037	4083	2	1	1001	1000	0	0	1	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	229	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	1	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4085
1004	4037	30	0	0	0	0	0	0	0	82	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlsl2 v0.2s, v1.2h, v2.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	0	712	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	64	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	441	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	64	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	106	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	64	10010	10	10000	10	10000	50	5706908	0	40018	40131	40084	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	2	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	12	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	41	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	311	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	2	16	2	2	39511	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	788	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	813	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlsl2 v0.2s, v0.2h, v1.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	0	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	313	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	724	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	183	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlsl2 v0.2s, v1.2h, v0.2h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	310	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	1	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	44	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	800	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39509	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	64	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40180	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	56	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	105	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1	536	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	12	0	0	61	39407	25	10036	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	3	39547	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl2 v0.2s, v8.2h, v9.2h
  movi v1.16b, 0
  fmlsl2 v1.2s, v8.2h, v9.2h
  movi v2.16b, 0
  fmlsl2 v2.2s, v8.2h, v9.2h
  movi v3.16b, 0
  fmlsl2 v3.2s, v8.2h, v9.2h
  movi v4.16b, 0
  fmlsl2 v4.2s, v8.2h, v9.2h
  movi v5.16b, 0
  fmlsl2 v5.2s, v8.2h, v9.2h
  movi v6.16b, 0
  fmlsl2 v6.2s, v8.2h, v9.2h
  movi v7.16b, 0
  fmlsl2 v7.2s, v8.2h, v9.2h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	48	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10138	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80100	100	80000	118	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	339	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	432	0	84	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	15	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	297	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	40	25	80233	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	336	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	465	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	219	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20069	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10027	3	1	1	9	25	2	2	1	5	6	20049	2	20	1	160000	10	20053	20053	20053	20053	20062
160024	20052	150	0	0	51	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	5	25	2	1	1	3	5	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	151	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20061	1	1	160021	10	9	10	10	160000	10	0	0	10033	6	1	1	7	25	4	1	2	7	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20121
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	3	25	2	1	1	5	5	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	3	25	2	1	1	3	5	20049	2	20	2	160000	10	20053	20053	20062	20062	20053
160024	20061	150	0	147	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	8	2	1	3	25	2	1	1	5	7	20058	2	20	1	160000	10	20053	20122	20062	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	8	2	1	6	24	2	1	1	3	5	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	210	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10028	8	2	1	5	25	2	1	1	3	5	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	331	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20061	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	1	0	10026	8	2	1	8	25	2	1	1	5	6	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	141	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20233	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	10026	8	2	1	3	25	2	1	1	3	5	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 12

Code:

  fmlsl2 v0.2s, v12.2h, v13.2h
  fmlsl2 v1.2s, v12.2h, v13.2h
  fmlsl2 v2.2s, v12.2h, v13.2h
  fmlsl2 v3.2s, v12.2h, v13.2h
  fmlsl2 v4.2s, v12.2h, v13.2h
  fmlsl2 v5.2s, v12.2h, v13.2h
  fmlsl2 v6.2s, v12.2h, v13.2h
  fmlsl2 v7.2s, v12.2h, v13.2h
  fmlsl2 v8.2s, v12.2h, v13.2h
  fmlsl2 v9.2s, v12.2h, v13.2h
  fmlsl2 v10.2s, v12.2h, v13.2h
  fmlsl2 v11.2s, v12.2h, v13.2h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	312	12	0	0	373	35689	25	120101	100	120000	100	120000	500	5966386	1	40020	0	40265	41686	24932	3	26644	120100	200	120223	200	360609	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	0	120000	100	41687	40040	41687	40040	41687
120204	41691	300	0	0	3	61	9961	25	120101	100	120000	100	120000	500	5630640	0	42451	0	41686	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	42461	0	120000	100	40092	40040	40040	40040	40040
120204	41686	300	0	0	1	61	9961	25	120100	100	120000	100	120000	500	5851993	0	41672	0	40039	40039	24932	3	26649	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41692	42471	40040	40040
120204	40039	299	0	0	0	61	9961	25	120103	100	120003	100	120000	500	5851993	0	40020	0	40039	41686	24932	3	26649	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	0	120000	100	41692	40040	40040	41687	40040
120204	41686	300	0	0	3	536	40274	25	120101	100	120000	100	120000	500	5630640	0	41669	0	40039	40039	26577	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	0	120000	100	40040	41687	40040	41687	40040
120204	41686	300	0	0	0	61	35689	25	120100	100	120000	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	0	120000	100	41692	40040	40040	40040	41687
120204	41686	300	0	0	0	61	37966	25	120100	100	120002	100	120000	500	5630640	1	41672	0	40039	41686	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	0	120000	100	40040	40040	40040	40040	40040
120204	40039	312	0	0	3	61	37966	25	120103	100	120003	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	2	0	7610	1	16	1	1	41683	0	120000	100	40040	41692	40040	42471	40040
120204	41691	299	0	0	3	61	9961	25	120100	100	120000	100	120000	500	5630640	0	41667	0	41686	40039	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	1	0	7610	1	16	1	1	40030	0	120000	100	42471	40040	40040	42471	40040
120204	40039	312	0	0	1	156	35689	25	120101	100	120000	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41683	0	120000	100	40040	41692	40040	40040	41687

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	300	0	0	61	9961	25	120010	10	120000	10	120000	50	5860508	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	5	16	0	0	3	5	40030	120000	10	40040	41703	40040	40040	40040
120024	40039	299	0	0	1497	9961	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	3	16	0	0	3	5	40030	120000	10	41692	40040	40040	40040	40040
120024	40039	300	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	41669	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7555	0	5	16	0	0	5	3	40030	120000	10	40040	40040	40040	40040	40040
120024	40039	312	0	4	61	35689	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	41686	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	3	16	0	0	5	3	40030	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	5	16	0	0	5	3	40030	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	3	16	0	0	3	5	40030	120000	10	40040	40040	40040	41703	40040
120024	40039	300	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	5	16	0	0	5	3	41693	120000	10	40040	40040	41703	40040	40040
120024	40039	300	0	0	61	9961	25	120010	10	120000	10	120000	50	5860508	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	41686	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	3	16	0	0	3	5	41678	120000	10	40040	40040	40040	40040	40040
120024	42470	300	12	0	61	9938	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	26615	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	5	16	0	0	5	3	40030	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	40020	0	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7520	0	3	16	0	0	5	5	41693	120000	10	40040	40040	41687	40040	41692

FMLSL2 (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations