Firestorm: FMLSL2 (vector, 4S) measurements

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	103	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	48	61	3398	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	147	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	270	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlsl2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	126	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	7	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	720	0	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	6	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	718	0	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40083	40037	38115	7	38741	10100	200	10346	204	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	717	0	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	6	38740	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	1	1	1	717	0	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	6	38741	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40083	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	44	10100	100	10000	104	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	310	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	61	39407	40021	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	40021	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38781	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	3	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	0	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlsl2 v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40229	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39500	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40181	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	1158	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	9	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	3	640	2	16	2	2	39473	10000	10	40038	40038	40038	40084	40038
10024	40037	300	2	156	251	39380	25	10010	10	10000	10	10000	60	5708304	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40228	40038
10024	40037	299	0	12	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40230	40037	38151	16	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	3	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlsl2 v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	789	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	212	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	84	39371	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	1	0	0	126	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10252	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	233	39407	25	10100	121	10000	100	10000	623	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	258	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	33	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	191	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	4	710	2	16	2	2	39479	25	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	279	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	191	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	124	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	39473	2	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	211	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	160	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl2 v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  fmlsl2 v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  fmlsl2 v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  fmlsl2 v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  fmlsl2 v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  fmlsl2 v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  fmlsl2 v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  fmlsl2 v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	2	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	124	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20089	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160205	20076	151	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	12	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160202	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	40	25	80100	100	80000	100	80000	500	640000	20046	20157	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20073	150	0	1	0	0	0	0	88	25	80012	12	80000	12	80000	62	640000	1	1	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10060	3	1	1	0	30	22	1	31	1	34	21	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	0	0	0	0	1	46	25	80012	12	80000	12	80000	62	640000	1	1	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10061	3	1	1	1	21	22	1	28	1	27	34	20046	2	16	160000	10	20050	20050	20119	20050	20050
160024	20049	150	0	0	0	0	0	1	58	25	80012	12	80000	12	80000	62	640000	1	1	20030	20047	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	3	1	1	1	36	22	1	28	1	35	37	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	151	1	0	0	0	0	1	46	25	80012	12	80000	12	80000	62	640000	1	1	20149	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	3	1	1	0	20	22	1	32	1	37	26	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	1	0	0	1	167	25	80012	12	80000	12	80000	62	640000	1	1	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10044	3	1	1	0	37	22	1	25	1	36	37	20046	2	16	160000	10	20223	20050	20050	20050	20050
160024	20049	150	0	0	1	0	0	0	58	25	80012	12	80000	12	80000	62	640000	1	0	20030	20049	20049	0	3	23	80012	20	80000	20	240324	20049	20135	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	3	1	1	0	36	22	1	26	1	36	26	20046	2	16	160000	10	20050	20050	20050	20050	20048
160024	20049	150	0	1	0	0	0	1	58	25	80012	12	80000	12	80000	62	640000	1	1	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10063	3	1	1	0	36	22	3	22	1	34	37	20046	2	16	160000	10	20050	20050	20050	20052	20050
160024	20049	150	0	1	1	0	0	1	58	25	80012	12	80000	12	80000	62	640000	1	1	20034	20049	20053	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10060	3	1	2	0	36	26	1	21	1	38	38	20046	2	16	160000	10	20050	20050	20050	20050	20054
160024	20049	150	0	0	1	0	0	1	58	25	80012	12	80000	12	80000	62	640000	1	0	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10058	6	2	1	0	37	22	3	24	2	38	37	20046	2	16	160000	10	20050	20050	20050	20050	20054
160024	20049	150	0	1	0	0	0	1	58	25	80012	12	80000	12	80000	62	640000	1	0	20030	20049	20049	0	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10060	3	1	1	0	35	22	1	22	1	36	36	20046	2	16	160000	10	20050	20050	20050	20050	20133

Test 6: throughput

Count: 12

Code:

  fmlsl2 v0.4s, v12.4h, v13.4h
  fmlsl2 v1.4s, v12.4h, v13.4h
  fmlsl2 v2.4s, v12.4h, v13.4h
  fmlsl2 v3.4s, v12.4h, v13.4h
  fmlsl2 v4.4s, v12.4h, v13.4h
  fmlsl2 v5.4s, v12.4h, v13.4h
  fmlsl2 v6.4s, v12.4h, v13.4h
  fmlsl2 v7.4s, v12.4h, v13.4h
  fmlsl2 v8.4s, v12.4h, v13.4h
  fmlsl2 v9.4s, v12.4h, v13.4h
  fmlsl2 v10.4s, v12.4h, v13.4h
  fmlsl2 v11.4s, v12.4h, v13.4h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	41687	40039	1	1	120201	100	99	100	100	120000	100	0	7610	4	16	3	5	40030	120000	100	41692	40040	41692	40040	40040
120204	41686	300	0	0	251	9961	25	120101	100	120001	100	120000	500	5630640	0	40020	40039	40039	26582	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	7610	2	16	2	3	40030	120000	100	40040	41687	40040	41692	40040
120204	40039	312	0	0	89	9961	25	120100	100	120000	100	120000	500	5851869	0	40020	40039	40039	26582	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	7610	2	16	2	3	41683	120000	100	40040	41692	40040	41692	40040
120204	40039	313	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	41691	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	7610	3	16	3	2	40030	120000	100	40040	40040	41692	40040	41692
120204	41686	300	0	0	61	9961	25	120100	100	120000	100	120000	500	5851869	0	40020	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	2	1	120201	100	99	100	100	120000	100	0	7610	3	16	3	2	40030	120000	100	40040	41692	40040	41692	40040
120204	40039	312	0	1	61	37966	25	120101	100	120001	100	120000	500	5630640	0	41672	41691	40039	24932	3	24997	120100	200	120000	200	360000	42470	40039	1	1	120201	100	99	100	100	120000	100	0	7610	3	16	3	2	40603	120000	100	40040	41687	40040	41692	40040
120204	40039	300	0	0	61	9961	25	120100	100	120000	100	120000	500	5851869	0	40020	40039	41686	26582	3	26644	120100	200	120000	200	360000	40039	40091	1	1	120201	100	99	100	100	120000	100	0	7610	3	16	2	3	40030	120000	100	40040	41687	40040	41692	40040
120204	40039	300	0	0	61	9961	25	120100	100	120000	100	120000	500	5851869	0	40020	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	7610	3	16	3	3	40030	120000	100	42471	40040	41692	40040	40040
120204	41686	300	18	1	61	9961	25	120100	100	120003	100	120000	500	5630640	0	41667	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	7610	2	16	3	2	40030	120000	100	41692	40040	41692	40040	41687
120204	41691	300	0	1	586	37966	25	120101	100	120001	100	120000	500	5630640	0	40020	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	7610	3	16	2	3	40030	120000	100	41692	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	316	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	41686	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	5	16	2	1	1	7	5	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	41691	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	7	16	2	1	1	7	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	41702	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	5	16	2	1	1	7	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	312	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	41686	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	7	16	2	1	1	5	7	40030	20	10	5	120000	10	40040	41692	40040	41692	40040
120024	40039	299	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	42451	40039	40039	26604	3	25019	120010	20	120000	20	360000	40039	41701	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	7	16	4	2	1	5	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	6	1	1	7	16	4	2	1	7	5	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40090	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	6	2	2	7	16	4	1	2	5	7	40030	20	20	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	5	16	2	2	2	5	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	6	2	1	7	16	2	1	2	7	5	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	2	7	16	4	1	2	7	7	40030	20	10	9	120000	10	40040	40040	40040	40040	40040

FMLSL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations