Firestorm: FMLSL (by element, 2S) measurements

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	0	3	0	103	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	103	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	4	73	1	24	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	0	0	0	0	82	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	9	88	82	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1148	1000	3000	4037	4037	1	1	1001	1000	2	1	1	3588	0	73	1	24	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	61	3407	25	1000	1000	1148	531908	4053	4037	4037	3258	3	3895	1000	1000	3000	4083	4132	1	1	1001	1000	0	0	0	220	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	6	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	3660	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	21	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	739	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	4	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	229	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	147	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	147	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	235	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	166	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	298	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	1	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	149	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	84	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	12	0	0	84	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	0	9	0	147	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	124	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38787	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	4	39512	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	1	0	0	0	84	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40414	40452	38163	39	38835	11196	22	11289	20	33894	40455	40417	10	1	10021	10	9	10	10	10000	10	2	4	3	1	0	32253	2	815	5	113	4	4	39799	1	10000	10	40464	40463	40466	40230	40464
10024	40369	302	1	1	9	8	537	792	7902	39326	200	10064	10	10036	16	11332	50	5719472	1	40333	40463	40497	38144	42	38925	11303	22	11452	20	34371	40271	40416	10	1	10021	10	9	10	10	10000	10	0	0	2	0	2	39400	0	855	3	104	6	6	39869	0	10000	10	40560	40550	40557	40512	40547
10024	40555	303	1	1	6	11	1464	968	94	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	6	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39547	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlsl v0.2s, v0.2h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10125	100	10000	125	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	3	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	44	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38744	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	25	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40085
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10125	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	3	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38744	10125	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	726	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	66	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	81	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	162	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40085	301	1	0	1	267	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	438	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	285	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	255	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	60	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	1	0	0	103	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	3	640	2	16	2	2	39473	10000	10	40085	40085	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlsl v0.2s, v1.2h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	12	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	24	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	531	132	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	219	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	301	0	438	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	261	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	15	0	0	94	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	6	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	15	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	117	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	363	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	103	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40085	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	1	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40085	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl v0.2s, v8.2h, v9.h[1]
  movi v1.16b, 0
  fmlsl v1.2s, v8.2h, v9.h[1]
  movi v2.16b, 0
  fmlsl v2.2s, v8.2h, v9.h[1]
  movi v3.16b, 0
  fmlsl v3.2s, v8.2h, v9.h[1]
  movi v4.16b, 0
  fmlsl v4.2s, v8.2h, v9.h[1]
  movi v5.16b, 0
  fmlsl v5.2s, v8.2h, v9.h[1]
  movi v6.16b, 0
  fmlsl v6.2s, v8.2h, v9.h[1]
  movi v7.16b, 0
  fmlsl v7.2s, v8.2h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	39	40	25	80100	100	80000	100	80000	500	640000	0	0	5	20046	20065	20065	12	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	0	0	0	3	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	5	0	0	3	16	0	3	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10112	0	0	0	3	16	0	2	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	124	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	10113	0	0	0	3	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	468	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	0	0	0	3	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10112	0	0	0	2	16	0	2	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	6	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	0	0	0	3	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	0	0	0	2	16	0	2	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10113	0	0	0	2	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	399	40	25	80100	100	80000	100	80000	500	640000	0	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10112	0	0	0	2	16	0	3	3	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	18	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	2	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20049	20047	1	1	160021	10	9	10	10	160000	10	0	10040	3	1	1	19	22	2	1	1	12	17	20046	2	16	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	10040	3	1	1	19	22	1	1	1	17	18	20044	2	15	160000	10	20048	20048	20048	20048	20050
160024	20049	150	0	0	6	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20049	20047	3	23	80012	20	80000	20	240000	20049	20047	1	1	160021	10	9	10	10	160000	10	0	10037	3	2	1	15	22	2	1	1	16	14	20044	2	16	160000	10	20048	20052	20052	20048	20050
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20049	20049	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	10037	3	1	1	17	20	1	1	1	16	12	20044	2	15	160000	10	20050	20050	20048	20050	20050
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20030	20047	20049	3	23	80012	20	80000	20	240000	20049	20051	1	1	160021	10	9	10	10	160000	10	0	10038	3	1	1	16	20	2	1	1	19	16	20044	2	16	160000	10	20048	20050	20050	20050	20050
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20030	20047	20047	3	23	80012	20	80000	20	240000	20049	20047	1	1	160021	10	9	10	10	160000	10	0	10038	3	1	1	15	20	2	1	1	17	17	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80108	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	10040	3	1	1	18	20	1	1	1	15	17	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	151	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	10039	3	1	1	17	20	1	1	1	19	19	20044	2	16	160000	10	20050	20050	20048	20048	20048
160024	20049	150	0	0	21	0	88	148	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20051	20047	1	1	160021	10	9	10	10	160000	10	0	10041	3	4	1	17	20	2	1	1	12	18	20044	2	15	160000	10	20048	20048	20048	20048	20133
160024	20049	150	0	0	0	0	311	25	80012	12	80000	13	80108	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	1	10042	3	1	1	16	20	2	1	1	19	13	20044	2	15	160000	10	20048	20050	20050	20133	20048

Test 6: throughput

Count: 12

Code:

  fmlsl v0.2s, v12.2h, v13.h[1]
  fmlsl v1.2s, v12.2h, v13.h[1]
  fmlsl v2.2s, v12.2h, v13.h[1]
  fmlsl v3.2s, v12.2h, v13.h[1]
  fmlsl v4.2s, v12.2h, v13.h[1]
  fmlsl v5.2s, v12.2h, v13.h[1]
  fmlsl v6.2s, v12.2h, v13.h[1]
  fmlsl v7.2s, v12.2h, v13.h[1]
  fmlsl v8.2s, v12.2h, v13.h[1]
  fmlsl v9.2s, v12.2h, v13.h[1]
  fmlsl v10.2s, v12.2h, v13.h[1]
  fmlsl v11.2s, v12.2h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	41707	300	0	0	0	0	0	0	61	9961	25	120100	100	120001	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	41692	40040	41692	40040
120204	40039	300	0	0	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5857726	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	42471	40040	40040
120204	42470	300	0	0	0	0	0	0	61	9961	25	120101	100	120000	100	120000	500	5630640	1	40020	0	41691	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	41692	40040	40040
120204	40039	300	0	0	0	0	0	0	61	9938	25	120100	100	120000	100	120000	500	5630640	1	40020	0	42470	40039	24932	3	26649	120100	200	120000	202	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	41692	40040	40040	40040
120204	42470	300	0	0	0	0	0	0	61	9939	25	120100	100	120000	100	120000	500	5630640	1	40020	0	40039	40039	26582	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	41677	0	120000	100	40040	40040	40040	41692	40040
120204	40039	299	0	0	0	0	0	1	61	9961	25	120100	100	120000	100	120000	500	5860488	0	41667	0	40039	40039	26582	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	41692	40040	40040	40040	40040
120204	40039	300	0	0	0	0	0	0	61	37966	25	120101	100	120000	100	120000	500	5630640	1	41682	0	41691	40039	24932	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	40040	40040	40040
120204	40039	312	0	0	1	0	0	0	61	9961	25	120100	100	120001	100	120000	500	5630640	0	40020	0	40039	41686	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	40040	41692	40040
120204	40039	300	0	0	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	41691	24932	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	0	0	0	61	9961	25	120100	100	120002	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	2	16	2	2	40030	0	120000	100	40040	40040	42471	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3474

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	41701	300	0	0	0	0	0	0	0	67	9961	25	120010	10	120001	10	120000	50	5630640	2	1	41672	40039	40039	24955	3	26666	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	5	16	2	1	1	3	4	40030	0	20	10	0	120000	10	40040	40040	41692	40040	40040
120024	41691	300	0	0	0	9	0	0	0	67	9961	25	120011	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	5	4	40030	0	20	10	0	120000	10	40040	40040	40040	40040	40040
120024	41691	300	0	0	0	0	0	0	0	67	9961	25	120013	10	120000	10	120000	50	5630640	0	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	4	3	41678	0	20	10	5	120000	10	40040	40040	41687	40040	40040
120024	40305	311	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	3	16	2	1	1	4	3	40030	0	20	11	5	120000	10	40040	40040	40040	40040	40040
120024	42470	312	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	6	2	1	4	16	2	1	1	4	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	41693	300	0	0	0	0	0	0	0	73	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	4	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	41691	300	0	0	0	0	0	0	0	73	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	4	16	2	1	1	3	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	41687	312	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	0	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	5	16	2	1	1	3	4	40030	0	20	10	5	120000	10	40040	40040	40040	41692	40040
120024	40039	306	0	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	3	1	1	3	16	2	1	1	4	3	40030	0	40	20	9	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	0	0	0	100	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	26604	3	25019	120010	20	120000	20	360000	41691	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7524	6	2	2	5	16	4	2	2	3	4	40030	0	40	20	9	120000	10	40040	40040	40040	40040	40040

FMLSL (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations