Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLSL (by element, 2S)

Test 1: uops

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403731000301033407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038
100440373100000613407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038
1004403730000001033407251000100010005319084018403740373258338951000100030004037403711100110000000473124113473100040384038403840384038
100440373010000823407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038
1004403730000988823407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038
100440373000000613407251000100010005319084018403740373258338951148100030004037403711100110002113588073124113473100040384038403840384038
100440373000000613407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038
10044037300000061340725100010001148531908405340374037325833895100010003000408341321110011000000220073116113473100040384038403840384038
100440373000060613407251000100010005319084018403740373258338951000100030004037403711100110000003660073116113473100040384038403840384038
1004403730000210613407251000100010005319084018403740373258338951000100030004037403711100110000000073116113473100040384038403840384038

Test 2: Latency 1->1

Code:

  fmlsl v0.2s, v1.2h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000739394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710041622394790100001004003840038400384003840038
1020440037300000229394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710021622394790100001004003840038400384003840038
1020440037300000147394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710121632394790100001004003840038400384003840038
1020440037300000147394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710131622394790100001004003840038400384003840038
1020440037299000235394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710121622394790100001004003840038400384003840038
1020440037300000166394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710121622394790100001004003840038400384003840038
1020440037300000298394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710121622394791100001004003840038400384003840038
1020440037300000149394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000712121622394790100001004003840038400384003840038
102044003729900084394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710131622394790100001004003840038400384003840038
1020440037300120084394072510100100100001001000050057069084001840037400373810833874510100200100002003000040037400371110201100991001001000010000710131622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037299000090147394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006403163439473010000104003840038400384003840038
1002440037300000000124394072510010101000010100005057069081400184003740037381303387871001020100002030000400374003711100211091010100001000000006403163439512010000104003840038400384003840038
1002440037300101000843940725100101010000101000050570690814001840414404523816339388351119622112892033894404554041710110021109101010000102431032253281551134439799110000104046440463404664023040464
10024403693021198537792790239326200100641010036161133250571947214033340463404973814442389251130322114522034371402714041610110021109101010000100020239400085531046639869010000104056040550405574051240547
100244055530311611146496894394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000060006403163439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006404164339473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006403163339547010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006403163339473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006403163339473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000000006403163439473010000104003840038400384003840038

Test 3: Latency 1->2

Code:

  fmlsl v0.2s, v0.2h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003730006139407251012510010000125100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011631394790100001004003840038400384003840038
1020440037299061394074410100100100001001000050057069084001840037400373810833874410100200100002003000040037400371110201100991001001000010000710116113947925100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840085
102044003730006139407251010010010000100100005005706908400184003740037381083387451012520010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003730036139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387441012520010000200300004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
1020440037299072639407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000071011612394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000066613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
100244003730000081613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000162613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440085301101267613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037299000438613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000285613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000002557263940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
100244003730000060613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010010640216223947310000104003840038400384003840038
100244003730001001033940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010203640216223947310000104008540085400384003840038

Test 4: Latency 1->3

Code:

  fmlsl v0.2s, v1.2h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730001200613940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003730002400613940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003729905311320613940725101001001000010010000500570690814001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300021900613940725101001001000010010000500570690814001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373010438007263940725101001001000010010000500570690814001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300026100613940725101001001000010010000500570690814001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003730001500943940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010060007101161139479100001004003840038400384003840038
102044003730001500613940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300011700613940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037299036300613940725101001001000010010000500570690804001840037400373810833874510100200100002003000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309193f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
10024400373000010339407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037299006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104008540038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037300016139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037300008239407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037299006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100640216223947310000104003840038400854003840038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlsl v0.2s, v8.2h, v9.h[1]
  movi v1.16b, 0
  fmlsl v1.2s, v8.2h, v9.h[1]
  movi v2.16b, 0
  fmlsl v2.2s, v8.2h, v9.h[1]
  movi v3.16b, 0
  fmlsl v3.2s, v8.2h, v9.h[1]
  movi v4.16b, 0
  fmlsl v4.2s, v8.2h, v9.h[1]
  movi v5.16b, 0
  fmlsl v5.2s, v8.2h, v9.h[1]
  movi v6.16b, 0
  fmlsl v6.2s, v8.2h, v9.h[1]
  movi v7.16b, 0
  fmlsl v7.2s, v8.2h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008815039402580100100800001008000050064000000520046200652006512238010020080000200240000200652006511160201100991001001600001000010113000316033200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010113500316032200621600001002006620066200662006620066
16020420065151040258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010112000316023200621600001002006620066200662006620066
16020420065150040258010010080000124800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000310113000316033200621600001002006620066200662006620066
1602042006515046840258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010113000316033200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010112000216023200621600001002006620066200662006620066
16020420065150640258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010113000316033200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010113000216023200621600001002006620066200662006620066
16020420065151040258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010113000216033200621600001002006620066200662006620066
1602042006515039940258010010080000100800005006400000002004620065200653238010020080000200240000200652006511160201100991001001600001000010112000216033200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)030f181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200751502000462580012128000012800006264000011200282004720047323800122080000202400002004920047111600211091010160000100100403111922211121720046216160000102004820048200482004820048
160024200471500000462580012128000012800006264000011200282004720049323800122080000202400002004920049111600211091010160000100100403111922111171820044215160000102004820048200482004820050
160024200491500060462580012128000012800006264000011200282004920047323800122080000202400002004920047111600211091010160000100100373211522211161420044216160000102004820052200522004820050
160024200471500000462580012128000012800006264000011200282004920049323800122080000202400002004720047111600211091010160000100100373111720111161220044215160000102005020050200482005020050
160024200471500000462580012128000012800006264000011200302004720049323800122080000202400002004920051111600211091010160000100100383111620211191620044216160000102004820050200502005020050
160024200471500000462580012128000012800006264000011200302004720047323800122080000202400002004920047111600211091010160000100100383111520211171720044215160000102004820048200482004820048
160024200471500000462580012128010812800006264000011200282004720047323800122080000202400002004720047111600211091010160000100100403111820111151720044215160000102004820048200482004820048
160024200471510000462580012128000012800006264000011200282004720047323800122080000202400002004720047111600211091010160000100100393111720111191920044216160000102005020050200482004820048
16002420049150002108814880012128000012800006264000011200282004720047323800122080000202400002005120047111600211091010160000100100413411720211121820044215160000102004820048200482004820133
1600242004915000003112580012128000013801086264000011200282004720047323800122080000202400002004720047111600211091010160000101100423111620211191320044215160000102004820050200502013320048

Test 6: throughput

Count: 12

Code:

  fmlsl v0.2s, v12.2h, v13.h[1]
  fmlsl v1.2s, v12.2h, v13.h[1]
  fmlsl v2.2s, v12.2h, v13.h[1]
  fmlsl v3.2s, v12.2h, v13.h[1]
  fmlsl v4.2s, v12.2h, v13.h[1]
  fmlsl v5.2s, v12.2h, v13.h[1]
  fmlsl v6.2s, v12.2h, v13.h[1]
  fmlsl v7.2s, v12.2h, v13.h[1]
  fmlsl v8.2s, v12.2h, v13.h[1]
  fmlsl v9.2s, v12.2h, v13.h[1]
  fmlsl v10.2s, v12.2h, v13.h[1]
  fmlsl v11.2s, v12.2h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)030918191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
120204417073000000006199612512010010012000110012000050056306401400200400394003924932324997120100200120000200360000400394169111120201100991001001200001000000007610216224003001200001004004041692400404169240040
120204400393000000006199612512010010012000010012000050058577261400200400394003924932324997120100200120000200360000400394003911120201100991001001200001000000007610216224003001200001004004040040424714004040040
120204424703000000006199612512010110012000010012000050056306401400200416914003924932324997120100200120000200360000400394003911120201100991001001200001000000007610216224003001200001004004040040416924004040040
120204400393000000006199382512010010012000010012000050056306401400200424704003924932326649120100200120000202360000416864003911120201100991001001200001000000007610216224003001200001004004041692400404004040040
120204424703000000006199392512010010012000010012000050056306401400200400394003926582324997120100200120000200360000400394003911120201100991001001200001000000007610216224167701200001004004040040400404169240040
120204400392990000016199612512010010012000010012000050058604880416670400394003926582324997120100200120000200360000400394003911120201100991001001200001000000007610216224003001200001004169240040400404004040040
1202044003930000000061379662512010110012000010012000050056306401416820416914003924932324997120100200120000200360000416914003911120201100991001001200001000000007610216224003001200001004004040040400404004040040
120204400393120010006199612512010010012000110012000050056306400400200400394168624932324997120100200120000200360000400394169111120201100991001001200001000000007610216224003001200001004004040040400404169240040
120204400393000000006199612512010010012000010012000050056306400400200400394169124932324997120100200120000200360000416914003911120201100991001001200001000000007610216224003001200001004004040040400404004040040
120204400393000000006199612512010010012000210012000050056306400400200400394003924932324997120100200120000200360000416914003911120201100991001001200001000000007610216224003001200001004004040040424714004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3474

retire uop (01)cycle (02)03mmu table walk data (08)09181e1f373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
12002441701300000000067996125120010101200011012000050563064021416724003940039249553266661200102012000020360000400394003911120021109101012000010000000075223115162113440030020100120000104004040040416924004040040
12002441691300000900067996125120011101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223114162115440030020100120000104004040040400404004040040
12002441691300000000067996125120013101200001012000050563064001400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223114162114341678020105120000104004040040416874004040040
12002440305311000000067996125120010101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223113162114340030020115120000104004040040400404004040040
12002442470312000000067996125120010101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075226214162114440030020105120000104004040040400404004040040
12002441693300000000073996125120010101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223114162114440030020105120000104004040040400404004040040
12002441691300000000073996125120010101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223114162113440030020105120000104004040040400404004040040
12002441687312000000067996125120010101200001012000050563064001400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223115162113440030020105120000104004040040400404169240040
12002440039306000000067996125120010101200001012000050563064011400204003940039249553250191200102012000020360000400394003911120021109101012000010000000075223113162114340030040209120000104004040040400404004040040
120024400392990000000100996125120010101200001012000050563064011400204003940039266043250191200102012000020360000416914003911120021109101012000010000000075246225164223440030040209120000104004040040400404004040040