Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLS (by element, 2S)

Test 1: uops

Code:

  fmls v0.2s, v1.2s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403731006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730008234072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
10044037300025134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
1004403730006134072510001000100053190840184037403732583389510001000300040374037111001100000073116113473100040384038403840384038
100440373002076134072510001000100053330440184037403732583389510001163300040374037111001100000073116113473100040384038403840384038
10044037300015634072510001000109653190840184037403732583389510001000300040374037111001100021073116113473100040384038403840384038

Test 2: Latency 1->1

Code:

  fmls v0.2s, v1.2s, v2.s[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730006139407251010010010000100100005005706908140018400374003738115638740101002001000820030024400374003711102011009910010010000100011171800160039490100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738115738741101002001000820030024400374003711102011009910010010000100011171800160039489100001004003840038400384003840038
1020440037300456139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840038400384003840038
102044003729906139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840086400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840038400384003840038
102044003729906139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004008540038400384003840038
102044003730006139407251010010210000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071212162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000071012162239479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000000390613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216133947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104013240085400384003840086
1002440037300100017117616983938925100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020305164003740037111002110910101000010130640216223947310000104003840038400384003840038
100244003730000001207263940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300010000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038

Test 3: Latency 1->2

Code:

  fmls v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400834003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
10204400373000000061394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000000758132113947917100001004003840038400384003840038
1020440037299011118510410339407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
10204400372990000072639407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300100006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300009306139407251001010100001010000505706908400180400374003738135338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
1002440037300000034639407441001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003729900006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730001006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908400180400374003738130338767100102010000203000040037400371110021109101010000100000640316333947310000104003840038400384003840038

Test 4: Latency 1->3

Code:

  fmls v0.2s, v1.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100001470071011611394790100001004003840038400384003840038
1020440037299000001453940725101001001000010010000522570830404001840037400373810833874510100200100002003000040037400371110201100991001001000010000210071011611394790100001004003840038400384003840038
1020440037299000006139407251010010010000128100005005706908040018400374003738108338745101002001000020030000400374008411102011009910010010000100001380071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100001350071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100001350071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100001380171011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100001530071011601394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100001620071011611394790100001004003840038400384003840038
10204400373000000044139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100001920071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020430000400374003711102011009910010010000100001620071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400372990061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001001290640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001001440640316333947310000104003840038400384003840038
100244003730000349394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001001320640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400372990061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001001350640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001001200640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001001230640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001001470640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001001380640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001001320640316333947310000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.2s, v8.2s, v9.s[1]
  movi v1.16b, 0
  fmls v1.2s, v8.2s, v9.s[1]
  movi v2.16b, 0
  fmls v2.2s, v8.2s, v9.s[1]
  movi v3.16b, 0
  fmls v3.2s, v8.2s, v9.s[1]
  movi v4.16b, 0
  fmls v4.2s, v8.2s, v9.s[1]
  movi v5.16b, 0
  fmls v5.2s, v8.2s, v9.s[1]
  movi v6.16b, 0
  fmls v6.2s, v8.2s, v9.s[1]
  movi v7.16b, 0
  fmls v7.2s, v8.2s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200891500402880100100800001008000050064000002004620065200653238010020080000200240000200652006511160201100991001001600001000001011111611200621600001002006620066200662006620066
160204200651500402580100100800001008000050064000012004620065200653238010020080000200240000200652006511160201100991001001600001000001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100282401011111611200621600001002006620066200662006620066
160204200651500402580100100800001008000050064000012004620065200653238010020080000200240000200652006511160201100991001001600001000001011111611200621600001002006620066200662006620066
1602042006515004028801001008000010080000500640000020046200652006532380100200800002002400002006520065111602011009910010016000010044001011111611200621600001002006620066200662006620066
160204200651500402580100100800001008000050064000002004620065200653238010020080000200240000200652006511160201100991001001600001001001011111611200621600001002006620066200662006620066
160204200651500402580100100800001008000050064000002004620065200653238010020080000200240000200652006511160201100991001001600001000001011111611200621600001002006620066200662006620066
160204200651510515258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100014401011111611200621600001002006620066200662006620066
160204200651510612580100100800001008000050064000002004620065200653238010020080000200240000200652006511160201100991001001600001001001011111611200621600001002006620066200662006620066
160204201471510402580100100800001008000050064000002004620065200653238010020080000200240000200652006511160201100991001001600001004712301011111611200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)183a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420088150110005762780012128000012800006264000011020033200522005232380012208000020240000200522005211160021109101016000010001004681123252112122200492201160000102005320053200532005320053
16002420052151010001552780012128000012800006264000011020033200522005232380012208000020240000200522005211160021109101016000010001004481121252112221200492201160000102005320053200532005320053
1600242005215011000802780012128000012800006264000011020033200522005232380012208000020240000200522005211160021109101016000010291561004681123252112223200492201160000102005320053200532005320053
16002420052150100001302780012128000012800006264000010020033200522005232380012208000020240000200522005211160021109101016000010001004332121252112123200492201160000102005320053200532005320053
1600242005215023000682780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010001004683124252112323200492201160000102005320053200532005320053
16002420052150010001062780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010001004882123252112223200492201160000102005320053200532005320053
1600242005215011000682780012128000012800006264000010520033200522005232380012208000020240000200522005211160021109101016000010001004482123252112222200492201160000102005520055200532005320053
16002420052150220002222780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010001004531123252112623200492201160000102005320053200532005320053
16002420052150220001326980012128000012800006264000010520033200522005232380012208000020240000200522005211160021109101016000010001004531122252112222200492201160000102005320062200532005320053
160024200521501100088278001212800001280000626400001052003320052200523238001220800002024000020052200521116002110910101600001037121004682123252112323200492201160000102006220053200532005320062

Test 6: throughput

Count: 12

Code:

  fmls v0.2s, v12.2s, v13.s[1]
  fmls v1.2s, v12.2s, v13.s[1]
  fmls v2.2s, v12.2s, v13.s[1]
  fmls v3.2s, v12.2s, v13.s[1]
  fmls v4.2s, v12.2s, v13.s[1]
  fmls v5.2s, v12.2s, v13.s[1]
  fmls v6.2s, v12.2s, v13.s[1]
  fmls v7.2s, v12.2s, v13.s[1]
  fmls v8.2s, v12.2s, v13.s[1]
  fmls v9.2s, v12.2s, v13.s[1]
  fmls v10.2s, v12.2s, v13.s[1]
  fmls v11.2s, v12.2s, v13.s[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
120204400392990000900101699612512010110012000010012000050056306400400204168740039253703249971201002001200002003600004003941688111202011009910010012000010000000007610316114168201200001004004040040416894004040040
1202044003930010002640176399612512027910012000210012000050056306400400204003940492249323266491201002001200002003600004003940039111202011009910010012000010000000027610116114003001200001004056541688400404004040040
1202044003931200010016199612512026710012000010012000050056306401400204003940708249323249971201002001200002003600004080940039111202011009910010012000010000000007656116114003001200001004004040040416894004041689
1202044003930000000038299612512010110012000010012000050056306401400204233840039249323249971201002001200002003600004003941691111202011009910010012000010000000007610116114003001200001004004040040400404247140040
12020440039312000000055999612512010110012000010012000050056306401400204003941688249323249971201002001200002003600004003941688111202011009910010012000010000000007657116114169201200001004168941692417004170240040
120204400393130000000416996125120101100120000100120000500563064014002040039400392493216249971201002001200002003600004003941688111202011009910010012000010000000007610116114003001200001004004040040416894004041689
120204412163000000000210371992512010010012000010012000050058569421400204168840039265793266451201002001200002003600004168840525111202011009910010012000010000000007610116114168201200001004004040040416894004040040
12020441687300000000053499612512010010012000010012000050056306400400204003941688249323249971201002001200002003600004003941688111202011009910010012000010000000007610116114003001200001004168940040400404168840040
12020441687299000000164199612512010010012000010012000050056306401400204003941688249323249971201002001200002003600004003941688111202011009910010012000010000000007610116114003001200001004004041689400404004040040
12020440039300000000051399612512010110012000010012000054556306400400204168840039265643249971201002001200002003600004003941688111202011009910010012000010000200007610125114003001200001004004040452400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e373a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
120024400393000000143499961251200101012000010120000505630640115400200400394003924955326666120010201200002036000040039400391112002110910101200001000752232120162111717400301594120000104004040040400404004040040
12002440039299000071769961251200101012000010120000505630640115400200400394003924955325019120010201200002036000040039400391112002110910101200001000752281117162111917400301594120000104004040040400404004040040
12002440039300000071119961251200101012000010120000505630640005400200400394003924955325019120010201200002036000040039400391112002110910101200001000752282118162112018400301594120000104004040040400404004041687
12002440039299000062339961251200101012000010120000505630640105400200400394169124955325019120010201200002036000040039400391112002110910101200001000752232219162111817400301594120000104004040040400404004040040
12002441691300000061769961251200101012000010120000505630640115400200400394003924955325019120010201200002036000040039400391112002110910101200001000752282116162111515400301594120000104004040040400404004040040
12002440039299000092209961251200101012000010120000505630640115400200400394003924955325019120010201200002036000040039400391112002110910101200001000752281119162112019400301594120000104004040040400404004040040
12002440039300000061559961251200101012000010120000505630640110400200400394003924955325019120010201200002036000040039400391112002110910101200001000752281118162111918400301594120000104004040040400404004040040
12002440039300000061619961251200101012000010120000505630640105400200400394003924955325019120010201200002036000040039400391112002110910101200001000752282117162111918400301594120000104004040040400404004040040
120024400393000000719799612512001010120000101200005056306401154168204003940039249553250191200102012000020360000400394003911120021109101012000010007522112112162111716400301597120000104004041687400404004040040
12002440039299000051619961251200101012000110120000505630640015400200400394003924955327450120010201200002036000040039400391112002110910101200001000752281118162111718400301584120000104004040040400404004040040