Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLS (by element, 4H)

Test 1: uops

Code:

  fmls v0.4h, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10044037310208340725100010001000531908140184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
10044037310145340725100010001000531908140184037403732583389510001000300040374037111001100040073216223473100040384086403840384038
10044037300843407251000100011485319081401840844037325833895100010003000403740371110011000110373216223473100040384038403840384038
1004403730061340725100010001000531908140184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
1004403730061340725100010001000531908140184037403732583389510001000300040374037111001100000073223223473100040384038403840384038
1004403731084340725100010001000531908140184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
1004403730061340725100010001000531908040184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
10044037301561340725100010001000531908140184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
1004403730061340725100010001000531908040184037403732583389510001000300040374037111001100000073216223473100040384038403840384038
1004403730061340725100010001000531908140184037403732583389510001000300040374037111001100000073216223473100040384038403840384038

Test 2: Latency 1->1

Code:

  fmls v0.4h, v1.4h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03091e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000298394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710031633394790100001004003840038400384003840038
102044003730000061394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710031643394790100001004003840038400384003840038
102044003729900061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003730000161394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003730000061394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003729900061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003730000061394072510100100100001001000050057069081400184003740086381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003730000061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000030710131633394790100001004003840038400384003840038
1020440037299000145394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038
102044003729900061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000000710131633394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000145394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640416333947310000104003840038400384003840038
10024400373003061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640416333947310000104003840038400384003840038
100244003730000441394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316433947310000104003840038400384003840038
10024400372990061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400373010061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038
10024400372990061394072510010101000010100005057069081400180400374003738130033876710010201000020300004003740037111002110910101000010000640316333947310000104003840038400384003840038

Test 3: Latency 1->2

Code:

  fmls v0.4h, v0.4h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730000006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003729900006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
1020440037300000033639407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000107101161339479100001004003840038400384003840038
1020440037300000072639407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003729900006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101164139479100001004003840038400384003840038
1020440037300000072639407251010010010000100100005005706908400184003740037381083387451010020010000200300004003740037111020110099100100100001000007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003729906139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003730006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003730006139407251001010100001010000555706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003729906139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003729906139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162539473010000104003840038400384003840038
100244003730006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
1002440037300035339407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003731006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003730006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038
100244003729906139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010006402162239473010000104003840038400384003840038

Test 4: Latency 1->3

Code:

  fmls v0.4h, v1.4h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300156139407251010010010000100100005005706908040018400374008538108738762101002041000020030498400374003711102011009910010010000100000007103162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102162239479100001004003840038400384003840038
102044003729906139407251010010410000100100005005706908140018400374003738108338745101002001000020030000400794003711102011009910010010000100000007102162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000307102162239479100001004003840038400384003840038
102044003731106139407251013310010000100100005005706908140053400374017938115338745104232001000020030000400374003711102011009910010010000100131007102162239479100001004003840038400384003840038
1020440037300072639407251010010010000100100005005706908140018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102162239479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102492239479100001004003840038400384003840038
1020440037300156139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100000007102162239479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000072639407251001010100001010000505706908040018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018400374003738130033876710010201000020300004003740037111002110910101000010130640216223947310000104003840038400384003840038
10024400372996608239407251001010100001010000505706908040018400374003738130033876710010201000020300004008440037111002110910101000010000640216223947310000104003840038400384003840038
1002440037299006139407251001010100001010000505706908040065400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
1002440037299006139407251001010100001010000505706908040018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400372990025139407251001010100001010000505706908140018400374003738130033876710010201000020300004003740037111002110910101000010000640216223947310000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.4h, v8.4h, v9.h[1]
  movi v1.16b, 0
  fmls v1.4h, v8.4h, v9.h[1]
  movi v2.16b, 0
  fmls v2.4h, v8.4h, v9.h[1]
  movi v3.16b, 0
  fmls v3.4h, v8.4h, v9.h[1]
  movi v4.16b, 0
  fmls v4.4h, v8.4h, v9.h[1]
  movi v5.16b, 0
  fmls v5.4h, v8.4h, v9.h[1]
  movi v6.16b, 0
  fmls v6.4h, v8.4h, v9.h[1]
  movi v7.16b, 0
  fmls v7.4h, v8.4h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200911502740258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100601011121611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
160204200651500103258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065151040258010011180000100801095006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
1602042006515031240258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066
16020420065150040258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100001011111611200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242009115000462780012128000012800006264000011020033200522005203238001220800002024000020052200521116002110910101600001000100306311134412127200582401160000102006220053200622006220062
1600242006115100522980012128000012800006264000001020042200612005203238001220800002024000020061200521116002110910101600001000100371352625412128200492402160000102005320062200532006220053
16002420052151004629800121280000128000062640000011020042200612005203238001220800002024000020052200611116002110910101600001000100321352825412611200492201160000102006220053200622005320062
160024200521510052298001212800001280000626400000110200422005220061032380012208000020240000200522006121160021109101016000010001003813621225412712200492202160000102006220053200622006220062
16002420061150005229800121280000128000062640000011020042200612006103238001220800002024000020061200611116002110910101600001000100331662634422116200582402160000102006220062200622006220062
16002420061150005229800121280000128000062640000011020042200612006103238001220800002024000020061200611116002110910101600001000100371662734222611200492202160000102006220062200532006220053
1600242005215001593429800121280000128000062640000011020042200612006103238001220800002024000020061200611116002110910101600001000100321372734412711200582402160000102006220062200622006220062
16002420061150094629800121280000128000062640000111020051200522006103238001220800002024000020061200611116002110910101600001000100371672734422711200582402160000102006220062200622006220062
160024200611500052278001212800001280000626400000110200422006120061032380012208000020240000200522006111160021109101016000010001003816721234421712200582402160000102006220062200622005320062
16002420139150005229800121280000128000062640000000200512006120061032380012208000020240000200612006111160021109101016000010001003816621225221611200582202160000102006220053200622006220053

Test 6: throughput

Count: 12

Code:

  fmls v0.4h, v12.4h, v13.h[1]
  fmls v1.4h, v12.4h, v13.h[1]
  fmls v2.4h, v12.4h, v13.h[1]
  fmls v3.4h, v12.4h, v13.h[1]
  fmls v4.4h, v12.4h, v13.h[1]
  fmls v5.4h, v12.4h, v13.h[1]
  fmls v6.4h, v12.4h, v13.h[1]
  fmls v7.4h, v12.4h, v13.h[1]
  fmls v8.4h, v12.4h, v13.h[1]
  fmls v9.4h, v12.4h, v13.h[1]
  fmls v10.4h, v12.4h, v13.h[1]
  fmls v11.4h, v12.4h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)181e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
12020440039303000039061996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004004040040400404169240040
12020440039300000015061996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610516114003001200001004004040040400404004040040
12020440039300000012061996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004004040040400404004040040
1202044003930000000061996125120100100120000100120000500563064004167240039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004004040040400404004041692
1202044003930000000061996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004004040040400404004040040
1202044003931200000061996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004168741692400404247141692
1202044003931200000061996125120100100120000100120000500563064014002040039400392493232499712010020012000020036000040039416861112020110099100100120000100000007610116114003001200001004004040040400404004040040
12020440039300000000726996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004168740040400404004040040
1202044003930000000361996125120100100120000107120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100010007610116114003001200001004004040040400404004040040
1202044076129900000161996125120100100120000100120000500563064004002040039400392493232499712010020012000020036000040039400391112020110099100100120000100000007610116114003001200001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)031e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1200244003930000407996125120010101200001012000050563064010400204003940039249553250191200102012000020360000400394003911120021109101012000010000752051021623400300120000104004040040400404004040040
1200244003929900124996125120010101200001012000050563064000400204003940039249553250191200102012000020360000416914003911120021109101012000010000752000021633400300120000104004041692400404004040040
120024400393129061996125120010101200001012000050563064010400204003940039249553250191200102012000020360000400394003911120021109101012000010000752000031632400300120000104004040040400404004040040
120024400923130061996125120010101200001012000050563064015400204003940039249553250191200102012000020360000400394003911120021109101012000010000752002031623400300120000104004040040416924168740040
120024400393120061996125120010101200001012000050563064005400204003940039266043250191200102012000020360000400394003911120021109101012000010000752003031623400300120000104004040040400404004040040
12002441691299390124996125120010101200001012000050563064005400204003940039249553266711200102012000020360000400394138911120021109101012000010020752003032432400300120000104004040040400404004040040
120024400393130061996125120010101200001012000050563064010400204003940039249553250191200102012000020360000400394003911120021109101012000010000752050031623416780120000104004040040400404004040040
120024400393120061996125120010101200001012000050563064015400204003940039249553266661200102012000020360000400394003911120021109101012000010000752050041633400300120000104004040040400404004040040
1200244009030000536996125120010101200001012000050563064000400204003940039249553250191200102012000020360000400394003911120021109101012000010000752050031633400300120000104004040040400404004040040
120024400393000061996125120321101200011012000050585186905400204003940039249553250191200102012000020360000400394003911120021109101012000010000752003021632400300120000104004040040400404004040040