Firestorm: FMLS (by element, H) measurements

Code:

  fmls h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	84	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	4033	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	3	73	2	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmls h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	149	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3680	710	0	4	52	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	9	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	229	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	145	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	536	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	9	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	82	39407	45	10010	10	10000	10	10000	61	5709700	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	3	2	0	640	2	16	2	3	39473	0	10000	10	40038	40358	40074	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	45	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmls h0, h0, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	441	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	9	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	33	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	272	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	2	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	0	0	0	0	441	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3508	0	640	2	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	662	2	49	2	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	12	0	61	39407	25	10020	10	10000	12	10296	50	5706908	0	40018	40037	40084	38130	3	38787	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	1	1	0	0	108	61	39389	25	10010	10	10006	11	10000	55	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmls h0, h1, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40084	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	8	8	1188	704	0	7267	39325	204	10203	143	10054	146	11184	739	5719472	0	40018	40455	40420	38143	44	38893	11377	224	11321	234	34422	40466	40417	10	1	10201	100	99	100	100	10000	100	0	0	2	0	0	32125	2	0	914	2	88	2	3	39797	34	10000	100	40455	40420	40467	40467	40417
10204	40463	302	0	1	9	9	1341	704	1	7244	39335	225	10201	142	10054	149	11332	743	5719472	0	40368	40464	40518	38142	44	38888	11484	229	11481	230	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40133
10204	40037	299	0	0	0	0	0	0	0	126	39333	227	10203	145	10048	152	11184	736	5718242	0	40368	40515	40560	38140	49	38929	11685	237	11689	234	35277	40512	40562	11	1	10201	100	99	100	100	10000	100	2	2	0	0	0	37965	0	0	933	1	122	1	2	39905	40	10000	100	40646	40614	40610	40606	40609
10204	40613	304	0	1	13	13	1716	1056	1	10158	39299	278	10231	163	10078	159	11776	787	5723660	0	40438	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	2	0	874	1	89	1	3	39821	0	10000	100	40038	40038	40038	40038	40086
10204	40037	300	0	0	0	0	0	0	0	1302	39407	44	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38111	13	38801	11471	248	11149	234	34428	40506	40560	12	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	0	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40085	40038
10024	40037	300	1	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls h0, h8, v9.h[1]
  movi v1.16b, 0
  fmls h1, h8, v9.h[1]
  movi v2.16b, 0
  fmls h2, h8, v9.h[1]
  movi v3.16b, 0
  fmls h3, h8, v9.h[1]
  movi v4.16b, 0
  fmls h4, h8, v9.h[1]
  movi v5.16b, 0
  fmls h5, h8, v9.h[1]
  movi v6.16b, 0
  fmls h6, h8, v9.h[1]
  movi v7.16b, 0
  fmls h7, h8, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	0	0	0	40	25	80221	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	2	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	5	1	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	5	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	560	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	519	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	0	0	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20072	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	0	1	20032	20051	20051	3	23	80012	20	80000	20	240000	20047	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	6	1	23	31	24	4	2	1	13	13	20048	2	30	160000	10	20052	20052	20052	20052	20052
160024	20051	150	0	0	0	0	52	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	1	0	10037	3	1	20	9	20	2	1	1	10	20	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	12	527	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10036	3	1	22	14	23	2	1	1	11	19	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	360	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	20	13	20	2	1	1	9	12	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10037	3	1	24	10	20	2	1	2	9	13	20044	2	15	160000	10	20048	20048	20048	20048	20052
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	3	1	20	18	20	2	1	1	10	13	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10035	3	1	22	14	20	2	1	1	14	9	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	3	1	21	9	20	2	1	1	8	12	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20094	20047	20047	3	23	80012	20	80000	20	240000	20047	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	3	1	20	11	20	2	1	1	17	8	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	3	1	22	10	20	2	1	1	13	10	20044	2	15	160000	10	20048	20048	20048	20048	20048

Test 6: throughput

Count: 12

Code:

  fmls h0, h12, v13.h[1]
  fmls h1, h12, v13.h[1]
  fmls h2, h12, v13.h[1]
  fmls h3, h12, v13.h[1]
  fmls h4, h12, v13.h[1]
  fmls h5, h12, v13.h[1]
  fmls h6, h12, v13.h[1]
  fmls h7, h12, v13.h[1]
  fmls h8, h12, v13.h[1]
  fmls h9, h12, v13.h[1]
  fmls h10, h12, v13.h[1]
  fmls h11, h12, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	6	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	40030	120000	100	41692	40040	40040	40040	40040
120204	40039	299	0	0	0	0	61	37966	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41450	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	36	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	299	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	3	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	1	7610	1	16	1	1	40030	120000	100	41692	40040	40040	40040	41692
120204	41687	300	0	0	0	1	61	9961	25	120100	100	120000	100	120000	500	5851993	0	41672	0	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	56	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41692	40040	40040
120204	41686	300	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	41691	26582	3	26649	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	40030	120000	100	40040	41687	40040	41687	40040
120204	40039	299	0	0	0	0	61	37966	25	120103	100	120001	100	120000	500	5630640	0	40020	0	40039	41691	26582	3	26649	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	40040
120204	40039	300	0	0	0	0	61	35689	25	120101	100	120003	100	120000	500	5630640	0	40020	0	40039	40039	26582	3	26649	120100	200	120000	200	360000	41009	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7633	1	16	1	1	40030	120000	100	41692	40040	41692	40040	41692
120204	41691	300	0	0	0	0	61	37966	25	120101	100	120001	100	120000	500	5630640	0	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	1	16	1	1	41683	120000	100	40040	40040	40040	40040	41692

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	299	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	8	0	0	18	16	13	11	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	0	251	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	26	16	12	14	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	14	16	11	14	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	12	16	12	12	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	41691	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	41667	40039	40039	24954	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	1	0	0	0	7520	0	0	0	14	16	14	13	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	7	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	12	16	10	12	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	1	5	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	11	16	15	11	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	26671	120010	20	120000	20	360000	41701	41691	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	15	16	15	14	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	11	16	13	10	40030	0	0	0	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	0	61	9961	25	120010	10	120000	10	120000	50	5630640	0	0	41667	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7520	0	0	0	12	16	13	12	40030	0	0	0	120000	10	40040	40040	40040	40040	40040

FMLS (by element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations