Firestorm: FMLS (vector, 2D) measurements

Code:

  fmls v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	0	0	61	3407	25	1000	1000	1000	533304	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1043	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	864	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	103	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3480	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	75	6	16	5	5	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	12	0	233	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	6	16	6	6	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmls v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40227	1	1	10201	100	99	100	100	10000	100	0	0	710	1	7	25	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40037	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40227	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	4	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	6786	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	1605	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	31479	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	310	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	661	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmls v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	12	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	31956	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3560	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	133	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40071	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	6	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10263	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	1	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	536	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	6	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2929	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30516	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	30	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40085	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39547	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmls v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10719	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	600	220	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	723	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	669	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40181	40038	40085	40038	40038
10204	40037	300	0	0	61	39407	45	10133	100	10000	106	10444	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	61	39407	102	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	219	0	179	39389	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10605	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	258	0	103	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	31938	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	294	0	231	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40227	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	66	0	82	39407	25	10010	10	10000	10	10000	50	5706908	1	40158	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	270	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38844	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	39	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.2d, v8.2d, v9.2d
  movi v1.16b, 0
  fmls v1.2d, v8.2d, v9.2d
  movi v2.16b, 0
  fmls v2.2d, v8.2d, v9.2d
  movi v3.16b, 0
  fmls v3.2d, v8.2d, v9.2d
  movi v4.16b, 0
  fmls v4.2d, v8.2d, v9.2d
  movi v5.16b, 0
  fmls v5.2d, v8.2d, v9.2d
  movi v6.16b, 0
  fmls v6.2d, v8.2d, v9.2d
  movi v7.16b, 0
  fmls v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80107	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	39	0	0	82	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	202	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20150	151	0	0	0	40	25	80100	100	80000	100	80000	500	643456	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	4	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	1	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20050	150	2	0	0	52	25	80012	12	80000	12	80000	62	640000	1	1	20032	20053	20053	3	23	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	6	1	1	6	24	3	2	2	6	6	20048	2	31	160000	10	20052	20052	20048	20054	20054
160024	20053	150	0	0	0	81	25	80012	12	80000	12	80000	62	640000	2	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	3	1	1	8	20	2	1	1	8	8	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	12	0	46	25	80012	12	80000	12	80000	62	640000	2	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	3	1	1	5	20	2	1	1	6	7	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	46	25	80012	12	80000	12	80000	62	640000	2	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	3	1	1	5	20	2	1	1	5	5	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	46	25	80012	12	80000	12	80000	62	640000	2	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	3	1	1	5	20	2	1	1	6	5	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	46	25	80012	12	80000	12	80000	62	640000	0	1	20028	20053	20047	3	23	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	3	1	1	6	20	2	1	1	5	6	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	0	0	46	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	6	2	2	5	24	4	2	2	5	6	20048	2	30	160000	10	20048	20048	20048	20048	20048
160024	20047	151	0	0	0	88	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	3	2	2	5	26	3	2	2	8	5	20048	2	31	160000	10	20052	20052	20052	20052	20052
160024	20053	150	0	0	0	236	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	1	0	10029	3	1	1	5	20	2	1	1	7	8	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	151	0	0	0	52	25	80012	12	80000	12	80000	62	640000	1	1	20028	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	1	0	10031	3	1	2	5	24	4	2	2	5	6	20050	2	30	160000	10	20054	20052	20054	20054	20052

Test 6: throughput

Count: 16

Code:

  fmls v0.2d, v16.2d, v17.2d
  fmls v1.2d, v16.2d, v17.2d
  fmls v2.2d, v16.2d, v17.2d
  fmls v3.2d, v16.2d, v17.2d
  fmls v4.2d, v16.2d, v17.2d
  fmls v5.2d, v16.2d, v17.2d
  fmls v6.2d, v16.2d, v17.2d
  fmls v7.2d, v16.2d, v17.2d
  fmls v8.2d, v16.2d, v17.2d
  fmls v9.2d, v16.2d, v17.2d
  fmls v10.2d, v16.2d, v17.2d
  fmls v11.2d, v16.2d, v17.2d
  fmls v12.2d, v16.2d, v17.2d
  fmls v13.2d, v16.2d, v17.2d
  fmls v14.2d, v16.2d, v17.2d
  fmls v15.2d, v16.2d, v17.2d

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40158	300	0	0	42	0	25	160135	100	160000	100	160000	500	4811711	0	41226	40040	40040	19973	0	3	22252	160100	200	160000	200	480000	40040	42318	1	1	160201	100	99	100	100	160000	100	0	0	162	0	10110	2	16	1	1	42291	160000	100	41246	40041	40041	40041	41246
160204	40043	300	12	0	42	4695	25	160135	100	160035	100	160000	500	1280000	0	40021	41245	41245	19973	0	3	19998	160100	200	160000	200	480000	42294	40040	1	1	160201	100	99	100	100	160000	100	0	0	57	0	10110	1	16	1	1	40037	160000	100	41191	40041	42286	41206	42295
160204	41230	309	0	0	42	8896	25	160100	100	160000	100	160000	500	1280000	1	42275	41245	41245	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	41242	160000	100	40041	40041	40041	40041	42282
160204	40040	300	0	0	61	0	25	160100	100	160000	100	160000	500	1280000	0	40021	40040	40040	19973	0	3	21188	160100	200	160000	200	480000	40040	41245	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	41242	160000	100	40041	42295	40042	40041	40041
160204	40040	300	0	0	64	8896	25	160100	100	160035	100	160000	500	1280000	1	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	42319	40041	42319	40041
160204	40040	308	459	35	61	0	25	160100	100	160000	100	160000	500	1280000	0	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	41245	41245	1	1	160201	100	99	100	100	160000	100	0	0	210	0	10110	1	16	1	1	40037	160000	100	40041	40041	42295	40041	42295
160204	40040	300	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	0	40021	40040	40040	21151	0	3	19998	160100	200	160000	200	480000	41245	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	40037	160000	100	42319	40041	42319	40041	40041
160204	40040	300	0	0	61	0	25	160153	100	160053	100	160000	500	1280000	0	40021	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	40037	160000	100	40041	42295	41246	40041	40041
160204	40040	299	0	35	234	0	25	160100	100	160000	100	160000	500	1280000	0	41226	41245	40040	19973	0	3	21203	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	42315	160000	100	40041	42319	40041	42319	40041
160204	41202	300	0	0	707	0	25	160100	100	160000	100	160000	500	5868333	1	40021	40040	40090	19973	0	3	22276	160100	200	160000	200	480000	40040	42318	1	1	160201	100	99	100	100	160000	100	0	0	96	0	10110	1	16	1	1	40037	160000	100	40041	42295	41246	40041	41246

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40093	309	0	0	5108	0	25	160010	10	160000	10	160000	50	1280000	1	1	40021	41190	40040	19996	3	21170	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	25	16	2	1	1	22	21	40037	0	20	8	160000	10	40041	40041	41191	40041	40041
160024	40061	300	0	0	47	0	25	160010	10	160000	10	160000	50	1280000	1	0	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	21	20	40037	0	20	8	160000	10	40041	40041	40041	40041	40041
160024	40077	300	0	0	56	0	25	160010	10	160000	10	160000	50	1280000	1	0	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	180	0	10024	3	1	1	17	16	2	1	1	21	17	40037	0	40	8	160000	10	40041	40044	41228	41228	40041
160024	40043	299	0	0	47	0	25	160011	10	160022	10	160000	50	5715261	1	0	40021	40040	40040	21118	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	171	0	10022	6	2	1	19	16	4	1	1	13	23	40037	0	20	8	160000	10	40041	40041	40041	40041	40041
160024	40043	300	0	0	47	0	25	160010	10	160001	10	160000	50	1280000	1	1	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	17	16	2	1	2	20	16	40037	0	20	8	160000	10	40041	40041	40041	40041	40041
160024	40041	299	0	0	53	0	25	160010	10	160000	10	160000	50	1280000	0	1	40024	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	6	2	1	13	16	2	1	1	22	20	40037	0	20	8	160000	10	40041	40041	40041	40041	40041
160024	41209	308	0	0	47	0	25	160010	10	160000	10	160000	50	1816226	0	1	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	41190	40040	1	1	160021	10	9	10	10	160000	10	0	2	0	216	0	10022	6	1	2	19	16	2	1	1	22	18	40037	0	20	16	160000	10	40041	40041	40041	40041	40041
160024	41209	300	0	0	47	0	25	160010	10	160000	10	160000	50	1280000	1	0	40021	40040	40040	19996	3	20023	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	3	1	2	22	16	4	1	1	19	22	40037	0	40	8	160000	10	40041	40041	40041	40041	40041
160024	41209	299	0	0	53	0	25	160010	10	160000	10	160000	50	1280000	1	1	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1	10022	3	2	1	20	16	4	1	1	16	19	40037	0	20	16	160000	10	40041	40041	40041	40041	40041
160024	41209	299	0	0	47	0	25	160010	10	160000	10	160000	50	5715261	1	0	40021	40040	40040	19996	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	72	0	10022	3	1	2	21	16	2	2	1	22	23	40037	0	20	8	160000	10	40041	40041	40041	40041	40041

FMLS (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations