Firestorm: FMLS (vector, 4H) measurements

Code:

  fmls v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	18	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	7	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	15	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	14	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmls v0.4h, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10252	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	27	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40053	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30516	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39547	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	5	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmls v0.4h, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	710	1	16	3	1	39549	10000	100	40038	40086	40132	40132	40133
10204	40085	300	2	2	0	0	1188	39407	25	10100	100	10012	116	10148	522	5708304	1	40053	40037	40037	38112	3	38782	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	1	0	0	0	710	1	16	2	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	4	0	24	0	103	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	27	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	156	88	124	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	912	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10025	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	22	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	0	640	4	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30486	40132	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmls v0.4h, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	20	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	566	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	145	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40083
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	1	0	61	39407	25	10010	10	10000	10	10000	60	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	536	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	1	0	61	39407	25	10010	10	10000	10	10148	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.4h, v8.4h, v9.4h
  movi v1.16b, 0
  fmls v1.4h, v8.4h, v9.4h
  movi v2.16b, 0
  fmls v2.4h, v8.4h, v9.4h
  movi v3.16b, 0
  fmls v3.4h, v8.4h, v9.4h
  movi v4.16b, 0
  fmls v4.4h, v8.4h, v9.4h
  movi v5.16b, 0
  fmls v5.4h, v8.4h, v9.4h
  movi v6.16b, 0
  fmls v6.4h, v8.4h, v9.4h
  movi v7.16b, 0
  fmls v7.4h, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d2	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20078	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10114	0	3	16	2	0	4	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	0	5	16	0	0	4	5	20067	0	160000	100	20066	20066	20066	20071	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10114	0	5	16	0	2	4	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	515	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	0	0	10115	0	4	16	0	0	4	5	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	52	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	0	6	10115	0	5	16	0	0	5	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	6	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	0	5	16	0	0	4	5	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10114	0	3	16	0	0	4	5	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10114	0	5	16	0	0	3	5	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10115	0	4	16	0	0	5	4	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10114	0	5	16	0	0	4	5	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20076	151	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	3	1	1	8	25	2	1	1	4	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	312	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	3	1	2	4	25	2	1	1	3	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	151	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	2	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	4	25	2	1	1	4	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	1	4	25	2	1	1	4	4	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	9	0	0	46	27	80012	12	80000	12	80000	62	640000	2	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10030	3	1	1	4	25	2	1	1	4	4	20049	2	40	1	160000	10	20053	20053	20053	20053	20062
160024	20061	150	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20061	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	1	2	3	34	4	1	1	3	4	20049	2	20	1	160000	10	20053	20062	20062	20053	20062
160024	20052	150	0	0	0	0	0	52	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20061	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	21	0	0	10027	3	1	2	4	25	2	1	1	4	3	20049	2	20	1	160000	10	20062	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	0	1	20042	20052	20052	3	23	80012	20	80000	20	240000	20052	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	3	1	1	3	25	4	1	1	4	4	20049	2	20	1	160000	10	20062	20053	20053	20053	20053
160024	20052	150	0	0	378	0	0	80	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	3	2	1	4	25	4	2	1	3	4	20058	2	40	1	160000	10	20053	20062	20053	20053	20053
160024	20052	150	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10027	6	1	1	4	25	4	1	2	3	4	20049	2	20	2	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 16

Code:

  fmls v0.4h, v16.4h, v17.4h
  fmls v1.4h, v16.4h, v17.4h
  fmls v2.4h, v16.4h, v17.4h
  fmls v3.4h, v16.4h, v17.4h
  fmls v4.4h, v16.4h, v17.4h
  fmls v5.4h, v16.4h, v17.4h
  fmls v6.4h, v16.4h, v17.4h
  fmls v7.4h, v16.4h, v17.4h
  fmls v8.4h, v16.4h, v17.4h
  fmls v9.4h, v16.4h, v17.4h
  fmls v10.4h, v16.4h, v17.4h
  fmls v11.4h, v16.4h, v17.4h
  fmls v12.4h, v16.4h, v17.4h
  fmls v13.4h, v16.4h, v17.4h
  fmls v14.4h, v16.4h, v17.4h
  fmls v15.4h, v16.4h, v17.4h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40501	306	1	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	5868895	1	40021	0	40040	40040	21151	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	201	10110	1	16	1	1	40037	160000	100	41246	41246	40041	40041	40041
160204	42327	308	0	0	0	0	0	0	0	42	0	25	160100	100	160000	100	160000	500	1280000	1	42299	0	40040	42318	22222	0	3	21177	160100	200	160000	200	480000	42318	40040	1	1	160201	100	99	100	100	160000	100	0	0	144	10110	1	16	1	1	42315	160000	100	40041	42319	40041	40041	40041
160204	40040	316	0	0	0	0	0	0	0	61	0	25	160135	100	160000	100	160000	500	1280000	0	40021	0	41245	40040	19973	0	3	21203	160100	200	160000	200	480000	41245	40040	1	1	160201	100	99	100	100	160000	100	0	0	153	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	41246
160204	40040	300	0	0	0	0	0	53	0	924	0	25	160100	100	160000	100	160000	500	5856057	0	42308	0	42327	40040	19973	35	3	19998	160100	200	160000	200	480000	42318	40040	1	1	160201	100	99	100	100	160000	100	0	0	150	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	41246
160204	40040	300	0	0	0	0	0	80	0	61	0	25	160100	100	160070	100	160000	500	1280000	0	40021	0	40040	40040	21151	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	40037	160000	100	42319	40041	40041	40041	40041
160204	40043	317	0	0	0	0	0	0	0	65	8970	25	160100	100	160053	100	160000	500	1280000	0	40021	0	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	42318	40040	1	1	160201	100	99	100	100	160000	100	0	0	24	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	40041
160204	42285	300	0	0	0	0	0	0	0	42	0	25	160143	100	160043	100	160000	500	1280000	0	40021	0	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	42318	1	1	160201	100	99	100	100	160000	100	0	0	162	10110	1	16	1	1	40037	160000	100	40041	42319	40041	40041	40041
160204	42309	300	0	0	0	0	0	36	0	42	0	25	160100	100	160000	100	160000	500	1280000	0	40021	0	40041	42318	19973	0	3	19998	160100	200	160000	200	480000	42318	40040	1	1	160201	100	99	100	100	160000	100	0	0	144	10110	1	16	1	1	40037	160000	100	41246	41246	41246	40041	40041
160204	40040	309	0	0	0	0	0	53	0	536	8970	25	160153	100	160000	100	160000	500	5856057	0	40021	0	40040	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	41245	1	1	160201	100	99	100	100	160000	100	0	0	189	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	41246
160204	42295	317	0	0	0	0	0	0	0	42	8970	25	160153	100	160000	100	160000	500	1280000	0	41226	0	42296	40040	19973	0	3	19998	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	156	10110	1	16	1	1	40037	160000	100	40041	40041	40041	40041	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40040	307	1	0	0	0	0	0	0	0	0	0	47	0	25	160010	10	160000	10	160000	50	5868333	0	1	41207	41226	41226	19996	0	3	22298	160010	20	160000	20	480000	41226	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	6	4	2	1	21	16	2	2	2	26	34	40037	0	31	11	8	160000	10	40041	40043	40041	41227	41227
160024	40040	317	1	0	0	0	0	0	0	0	53	0	1134	0	25	160063	10	160053	10	160000	50	1280000	1	1	40021	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10025	6	4	2	1	33	16	3	2	2	33	35	40037	0	15	5	9	160000	10	40041	40041	42319	40041	40043
160024	40040	300	1	0	0	0	0	0	0	0	0	0	53	0	25	160010	10	160000	10	160000	50	1280000	1	1	40021	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	3	1	1	1	33	16	2	1	1	17	34	40037	0	15	5	9	160000	10	40041	42319	40041	40041	40041
160024	40042	316	1	0	0	0	0	0	0	0	53	0	712	0	25	160010	10	160000	10	160000	50	5728047	1	1	41200	40040	40040	19996	0	3	22298	160010	20	160000	20	480000	40040	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	3	1	1	1	34	16	2	1	1	33	34	42315	0	15	7	4	160000	10	40041	42319	40041	42319	42319
160024	42318	300	1	0	0	0	0	0	0	0	0	0	67	8863	25	160055	10	160053	10	160000	50	5868333	1	1	40021	42318	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	3	1	1	1	32	16	2	1	1	34	34	42315	0	15	6	11	160000	10	40041	42319	40041	40041	40041
160024	40040	300	1	0	0	0	0	0	0	0	0	0	47	8970	25	160010	10	160000	10	160000	50	1319999	1	1	40021	40040	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	1	10026	6	4	2	1	34	16	3	1	2	25	33	40037	0	31	22	17	160000	10	40637	42319	40041	40041	40041
160024	40040	300	1	0	0	0	0	0	0	0	53	1	59	0	25	160010	10	160053	10	160000	50	1280000	1	1	40021	40040	42318	22244	0	3	20020	160010	20	160000	20	480000	41226	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	6	4	2	1	33	16	3	2	2	32	35	40037	0	31	11	11	160000	10	40041	42319	40041	40041	40041
160024	40040	300	1	0	0	0	0	0	0	0	53	1	73	0	25	160010	10	160053	10	160000	50	5728047	1	1	42266	42318	40040	19996	0	3	22298	160010	20	160000	20	480000	41226	41226	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10025	6	4	2	1	34	16	3	2	2	18	32	40037	0	31	11	12	160000	10	40041	40042	41220	41218	41227
160024	40040	300	1	0	0	0	0	0	0	0	0	0	67	0	25	160010	10	160000	10	160000	50	5868333	1	1	40021	40040	42318	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	3	1	1	1	18	16	2	1	1	33	32	40037	0	15	6	4	160000	10	40041	40041	40041	41230	41227
160024	41226	300	1	0	0	0	0	0	0	0	0	0	47	0	25	160010	10	160000	10	160000	50	1280000	1	1	41207	42318	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42318	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	3	1	1	1	35	16	2	1	1	17	33	42315	0	31	11	1	160000	10	42319	40041	40041	40041	40041

FMLS (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations