Firestorm: FMLS (vector, 4S) measurements

Code:

  fmls v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	103	3407	25	1000	1000	1000	531908	0	4018	4084	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	15	61	3407	25	1000	1000	1148	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	12	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	24	6	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	124	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	103	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	103	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmls v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10556	204	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	624	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	0	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	666	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	66	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30540	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	3	16	2	2	39475	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40085	300	0	0	0	0	18	0	0	1710	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40132	40037	38137	0	7	38843	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	6	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40085	40038	40038	40038
10024	40037	299	0	0	0	0	60	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10006	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40076	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmls v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	39489	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38115	7	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	39489	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	9	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	5877	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	3	42	176	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	150	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	9	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	62	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	91	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	25	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40085	300	0	84	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	171	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmls v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	12	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	60	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	126	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	130	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40070	1	1	10021	10	9	10	10	10000	10	0	0	0	33	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40085	40038
10024	40037	299	1	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	30	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40085	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10157	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	15	640	2	16	2	2	39545	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	27	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	21	640	2	16	6	6	39475	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	27	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	24	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmls v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  fmls v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  fmls v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  fmls v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  fmls v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  fmls v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  fmls v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  fmls v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20077	151	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	24	10112	5	0	3	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	3	10112	0	1	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	0	1	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	7	0	10112	5	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	5	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	0	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	0	1	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	5	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	325	25	80100	100	80000	100	80000	500	640000	1	0	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	4	0	10112	0	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	0	5	20046	0	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	0	100	100	160000	100	0	0	10112	0	0	2	16	2	2	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20100	150	2	3	0	0	0	852	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	1	1	24	25	2	1	1	17	15	20049	2	20	1	160000	10	20053	20062	20062	20062	20062
160024	20052	150	1	0	0	0	0	837	27	80012	12	80000	12	80000	62	640000	0	1	5	20042	20061	20061	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10037	8	3	2	15	34	4	1	1	14	16	20058	2	20	1	160000	10	20062	20053	20053	20053	20053
160024	20052	150	1	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20061	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10037	8	4	1	16	25	2	1	1	16	15	20049	2	20	1	160000	10	20053	20053	20053	20053	20062
160024	20052	150	0	1	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	1	10039	8	5	1	10	25	2	1	1	16	16	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	1	0	0	0	1186	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	5	1	17	25	4	2	1	10	17	20058	2	20	1	160000	10	20053	20053	20053	20062	20062
160024	20061	150	1	2	0	0	1	1096	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	5	1	16	25	2	1	1	15	15	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	1	0	0	0	1536	27	80012	12	80000	12	80000	62	640000	0	1	5	20042	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10037	8	5	1	10	25	2	1	1	10	15	20049	2	20	1	160000	10	20053	20062	20053	20053	20053
160024	20052	150	1	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10040	8	5	1	16	25	2	1	1	16	17	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	2	1	0	0	0	984	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	21	0	0	10038	8	6	1	15	25	2	2	1	16	17	20058	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	5	1	13	25	2	1	1	16	10	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 16

Code:

  fmls v0.4s, v16.4s, v17.4s
  fmls v1.4s, v16.4s, v17.4s
  fmls v2.4s, v16.4s, v17.4s
  fmls v3.4s, v16.4s, v17.4s
  fmls v4.4s, v16.4s, v17.4s
  fmls v5.4s, v16.4s, v17.4s
  fmls v6.4s, v16.4s, v17.4s
  fmls v7.4s, v16.4s, v17.4s
  fmls v8.4s, v16.4s, v17.4s
  fmls v9.4s, v16.4s, v17.4s
  fmls v10.4s, v16.4s, v17.4s
  fmls v11.4s, v16.4s, v17.4s
  fmls v12.4s, v16.4s, v17.4s
  fmls v13.4s, v16.4s, v17.4s
  fmls v14.4s, v16.4s, v17.4s
  fmls v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40578	317	0	0	0	0	0	43	0	563	4489	25	160100	100	160080	100	160000	500	5707497	40021	40040	42312	22214	0	3	22285	160100	200	160000	200	480000	40041	40041	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40039	0	160000	100	41210	40041	40041	42326	40041
160204	40040	300	0	0	0	0	0	34	0	913	0	25	160101	100	160000	100	160000	500	5745006	40023	40040	42327	21115	0	3	21167	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40039	0	160000	100	41210	41210	41210	41210	40043
160204	40042	317	0	0	0	0	0	0	0	344	8988	25	160168	100	160000	100	160000	500	1280000	41190	40040	41190	22198	0	3	19998	160100	200	160000	200	480000	40040	42312	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40037	0	160000	100	41210	41210	41210	41210	40041
160204	40040	300	0	0	0	0	0	0	0	408	8988	25	160134	100	160019	100	160000	500	5707386	41190	42327	41204	19973	0	3	21162	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	42324	0	160000	100	42295	42299	40041	42313	42295
160204	42294	317	0	0	0	0	0	1	1	524	4695	25	160134	100	160000	100	160000	500	5864245	40021	42325	41209	21095	0	3	21167	160100	200	160000	200	480000	41209	41209	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40037	0	160000	100	40043	41205	41206	40041	40043
160204	40040	300	0	0	0	0	0	0	0	42	4575	25	160140	100	160061	100	160000	500	5705774	40021	40040	40040	20240	35	3	20000	160100	200	160000	200	480000	42315	41209	1	1	160201	100	99	100	100	160000	100	0	0	0	0	6	10110	2	16	2	3	41206	0	160000	100	41210	41210	41210	40041	41210
160204	40042	317	0	0	0	0	0	0	0	187	4695	25	160140	100	160141	100	160000	629	5865526	40863	41269	41205	21109	0	3	21239	160100	200	160000	200	480000	40042	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10143	2	16	2	2	42322	0	160000	100	42326	41210	40041	42319	40041
160204	42335	300	0	0	0	0	0	68	0	336	0	25	160180	100	160034	100	160000	500	5707386	41190	40042	40040	19973	0	3	21167	160100	200	160000	200	480000	40042	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40037	0	160000	100	42315	40041	42326	41210	41205
160204	41205	317	0	0	0	0	0	0	0	345	0	25	160168	100	160000	100	160000	500	5707497	40021	40040	42298	22205	0	3	21239	160100	200	160000	200	480000	40042	40042	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40037	0	160000	100	40041	41191	40043	41282	40041
160204	41198	300	0	0	0	0	0	0	0	126	0	25	160134	100	160068	100	160000	500	5865526	41185	40042	41204	19973	0	3	19998	160100	200	160000	200	480000	40043	42296	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	2	2	40039	0	160000	100	40041	40041	42326	41210	41206

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2592

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	80	406	0	25	160090	10	160070	10	160000	50	1319999	0	1	5	40021	40443	40040	22237	33	3	20023	160010	20	160000	20	480000	42327	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	2	1	3	16	2	2	3	5	8	42324	15	7	0	160000	10	42328	42328	40041	42328	42328
160024	40040	316	0	0	0	218	8955	25	160090	10	160080	10	160000	50	1280000	1	1	5	42308	42327	40040	19996	0	3	22307	160010	20	160000	20	480000	41205	42285	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	3	1	6	16	2	1	1	6	3	40037	15	5	0	160000	10	42328	40041	42328	42328	40041
160024	40040	316	0	0	0	236	8863	25	160010	10	160000	10	160000	50	1280000	1	1	5	42308	42294	42327	22237	33	3	22307	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	6	16	2	1	1	6	4	42324	15	6	0	160000	10	42328	40041	42328	40041	42328
160024	42327	300	0	0	80	200	8955	25	160090	10	160080	10	160000	50	5868895	1	1	5	42308	40040	42327	22237	33	3	22307	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	5	16	2	2	1	5	5	42332	15	5	0	160000	10	42328	40041	42328	40041	42328
160024	42327	317	0	0	0	197	0	25	160090	10	160000	10	160000	50	1280000	1	1	5	42308	40040	42327	22237	33	3	22307	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	4	16	2	1	1	4	7	42324	15	5	0	160000	10	40041	42315	42328	40041	40041
160024	40040	317	0	0	0	474	0	25	160090	10	160000	10	160000	50	1280000	1	1	5	40021	42327	42327	22237	33	3	20020	160010	20	160000	20	480000	42327	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	5	16	2	1	1	5	5	40037	15	5	0	160000	10	40041	42328	40041	42328	42328
160024	42327	300	0	0	0	265	8955	25	160010	10	160000	10	160000	50	5868895	1	1	5	40021	42327	40040	22237	33	3	20020	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	3	16	2	1	1	5	3	42324	15	6	0	160000	10	42328	40041	42328	42286	40041
160024	42327	317	0	0	0	216	0	25	160090	10	160080	10	160000	50	1280000	1	1	5	42295	42327	40040	19996	0	3	20020	160010	20	160000	20	480000	40040	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	7	16	2	1	1	7	8	42324	15	5	0	160000	10	42328	42328	42328	42328	42328
160024	42327	299	0	0	0	177	8955	25	160010	10	160000	10	160000	50	5868895	1	1	5	40021	42327	40040	22237	33	3	22307	160010	20	160000	20	480000	42327	42327	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	6	16	2	1	1	7	4	40037	15	5	0	160000	10	42328	42000	40041	42328	40041
160024	42327	317	0	0	0	110	8955	25	160010	10	160000	10	160000	50	5868895	1	1	5	40021	42285	40040	19996	33	3	20020	160010	20	160000	20	480000	42327	40040	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	8	5	1	7	16	2	1	1	7	4	40037	15	6	0	160000	10	40041	42328	40041	42328	42328

FMLS (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations