Firestorm: FMOV (D[1] from X) measurements

Code:

  fmov v0.d[1], x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2101	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	186	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	15	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	0	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	3	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041
2004	2040	16	0	2025	1690	25	2000	1000	1000	1000	1000	6342	265147	1	2021	2040	2040	1450	3	1773	2000	1000	1000	1000	2000	2040	2040	1	1	1001	1000	1000	0	0	73	1	16	1	1	2037	1000	1000	2041	2041	2041	2041	2041

Test 2: Latency 1->2 roundtrip

Code:

  fmov v0.d[1], x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	120035	930	0	0	0	0	0	12	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735720	13672053	0	120013	0	120032	120032	115534	6	116236	30100	200	10003	20005	200	10003	30008	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	119586	10000	0	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	931	0	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120088	120036	115527	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10004	0	1	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	930	0	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120033	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	931	0	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120014	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120033	120033	120033
30204	120032	930	0	0	0	0	0	12	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120034	120033	120033	120033	120033
30205	120032	931	0	0	0	0	0	0	0	0	120017	109457	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120033	120033	120037
30204	120032	931	0	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120035	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10004	0	0	0	8138	2	0	0	0	1310	1	3	16	2	2	119574	10000	0	10000	10000	10100	120033	120041	120033	120033	120033
30204	120032	930	0	1	1	2	0	0	0	0	120017	109659	128	40140	10125	20004	10008	112	20460	10198	563	5750320	13699490	0	120382	0	120501	120210	115525	27	116297	30100	200	10000	20000	200	10000	30000	120034	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120043	120033	120033	120033	120033
30204	120032	931	0	0	0	0	0	0	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	0	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	0	1	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120125	120039	120034
30204	120032	931	0	0	0	0	0	12	0	0	120017	109456	25	40100	10100	20000	10000	100	20000	10000	500	5735672	13672053	1	120013	0	120032	120032	115525	3	116240	30100	200	10000	20000	200	10000	30000	120032	120032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	119574	10000	0	10000	10000	10100	120033	120033	120034	120033	120033

1000 unrolls and 10 iterations

Result (median cycles for code): 12.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	120032	930	0	0	0	0	12	0	120022	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	1270	2	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	931	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115625	3	116262	30177	20	10000	20000	20	10066	30000	120037	120198	2	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120034	930	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115581	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	931	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120014	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	930	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5736378	13670029	1	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	931	0	0	0	4	0	0	120017	109456	25	40042	10010	20000	10008	10	20000	10197	50	5735672	13670029	1	120307	0	120032	120032	115548	3	116486	30010	20	10243	20000	20	10245	30000	120032	120395	1	1	20021	10	9	10	10010	10000	10	2	0	10006	0	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120386	120033	120392
30024	120032	931	0	0	0	0	0	352	120017	109526	25	40010	10020	20000	10000	12	20000	10000	50	5735672	13670029	1	120321	0	120032	120032	115548	26	116262	30010	20	10000	20000	22	10000	30000	120359	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	930	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5735672	13670029	1	120013	0	120032	120032	115548	3	116262	30010	22	10000	20000	20	10000	30000	120032	120032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	119574	10000	0	10000	10000	10010	120033	120033	120033	120033	120033
30024	120032	931	0	0	0	0	0	0	120017	109456	25	40010	10010	20000	10000	10	20000	10000	50	5737592	13671830	0	120013	0	120032	120032	115548	3	116262	30010	20	10000	20000	20	10921	34542	122219	122057	27	1	20021	10	9	10	10010	10000	10	7	4	10047	1	0	91603	0	1786	3	267	1	1	119574	10000	0	10000	10000	10010	120625	120033	121876	122000	122187
30024	122084	943	1	1	23	28	3708	1936	122457	110481	635	40242	10065	20116	10020	10	20000	10000	50	5735672	13670029	0	120013	0	121957	121975	116453	167	117828	34633	24	11717	20482	20	10000	30000	120102	122342	34	1	20021	10	9	10	10010	10000	10	4	2	10049	1	2	131471	0	1664	5	237	1	1	119574	10007	0	10000	10000	10010	121894	121998	121986	122050	120033

Test 3: throughput

Count: 8

Code:

  fmov v0.d[1], x8
  fmov v1.d[1], x8
  fmov v2.d[1], x8
  fmov v3.d[1], x8
  fmov v4.d[1], x8
  fmov v5.d[1], x8
  fmov v6.d[1], x8
  fmov v7.d[1], x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	26711	207	0	0	0	327	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6661	160135	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	1	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26713	26709	26709	26709
160204	26708	207	0	0	0	3	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26690	26708	26708	6632	0	6	6666	160136	200	80024	80024	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	3	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6666	160135	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	348	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6660	160135	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26709	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	330	0	26693	3	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6635	0	6	6665	160135	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	1	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	303	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6657	160134	200	80020	80024	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	282	0	26694	2	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26693	26708	26708	6632	0	6	6659	160135	200	80024	80020	200	80020	160048	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	3	0	1	1	1	5117	0	16	0	0	26706	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	0	0	0	384	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6657	160136	200	80020	80020	200	80024	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26714	26709	26712	26709	26713
160204	26718	206	0	0	0	0	0	26693	0	25	160100	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6660	160135	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	0	1	1	1	5117	0	16	0	0	26705	0	80000	80000	100	26709	26709	26709	26709	26709
160204	26708	207	1	0	0	336	372	26693	0	25	160884	100	80000	80000	100	80020	80015	500	1168951	1898016	0	0	26689	26708	26708	6632	0	6	6659	160134	200	80020	80020	200	80020	160040	26708	26708	1	1	80201	100	99	100	100	80000	100	2	0	0	80000	0	0	2598	0	1	1	1	5161	0	16	0	0	26705	0	80000	80000	100	26709	27199	26709	26709	26709

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	26708	200	0	0	48	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	3	1	0	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	0	0	3	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1890591	4	1	5	26706	26708	26708	6673	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	4	0	136	80000	3	0	0	5020	0	0	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26696	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	8	1	0	26691	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	5	0	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	144	88	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1891229	7	1	0	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	0	0	1	16	1	1	26705	80000	80000	10	27205	26718	26716	26722	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	7	1	5	26696	26719	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	5	4	1	16	1	2	26712	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1169025	1897622	7	1	0	26691	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	5	0	1	16	1	1	26721	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	7	1	0	26695	26709	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160378	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	5	4	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	8	1	0	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26712	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	0	0	3	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	0	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	7	1	0	26689	26708	26708	6653	0	3	6693	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	1	12	0	5020	0	0	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709
160024	26708	200	0	0	12	0	26693	0	25	160010	10	80000	80000	10	80000	80000	50	1168880	1897931	7	1	0	26689	26708	26708	6653	0	3	6688	160010	20	80000	80000	20	80000	160000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	0	80000	0	0	0	5020	0	0	1	16	1	1	26705	80000	80000	10	26709	26709	26709	26709	26709

FMOV (D[1] from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations