Firestorm: FMOV (D[1] to X) measurements

Code:

  fmov x0, v0.d[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	1	0	88	138	25	2000	1000	1000	1081	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	2	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	5	0	57	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	15	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	75	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	5	0	0	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  fmov x0, v0.d[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e4	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	775	0	0	0	0	204	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100044	100379	96900	3	97498	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100042	100039	100039	100039	100039
20204	100379	775	0	0	0	0	0	0	0	100023	89564	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	2	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100039	100039	100039	100225
20204	100038	775	0	0	0	0	12	0	0	100023	89562	25	30100	10100	10000	10000	100	10056	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	3	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96904	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	15	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100039	100039	100039	100040
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	1	3	0	0	1329	1	2	16	2	2	99637	0	10000	10000	10100	100039	100041	100041	100039	100131
20204	100045	776	0	1	0	1	0	0	0	100023	89561	43	30100	10133	10000	10004	105	10179	10050	500	4784587	5580459	0	100013	0	100122	100041	96903	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100042	100045	100118	100039	100039
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100016	0	100038	100038	96942	3	97496	20100	200	10000	10000	200	10000	10000	100041	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	3	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100039	100039	100039	100039
20204	100041	776	0	1	1	3	567	0	0	100369	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580406	0	100013	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100040	100038	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	1310	1	2	16	2	2	99637	0	10000	10000	10100	100039	100042	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	0	100039	100038	96900	3	97496	20100	200	10000	10000	200	10000	10059	100039	100038	1	1	20201	100	99	100	10100	10000	100	2	10000	0	9	0	0	1311	1	2	16	2	2	99637	0	10000	10000	10100	100040	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	775	0	0	0	0	0	0	100024	89621	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	6	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100071	100039
20024	100038	775	0	0	0	0	12	0	100026	89628	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100039	96922	3	97520	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100098	100039
20024	100038	775	0	0	0	0	0	0	100024	89599	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579008	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	1298	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	100023	89647	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100042	100040	100039	100039
20024	100038	775	1	0	0	0	18	0	100023	89591	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	100023	89637	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96923	3	97518	20010	20	10000	10000	20	10000	10000	100038	100040	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100043	100039	100039
20024	100038	776	0	0	0	0	12	0	100023	89584	25	30010	10010	10000	10000	10	10234	10000	50	4778481	5578954	0	100016	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100104	100039
20024	100038	775	0	0	0	0	12	0	100023	89620	31	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100040	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	100023	89646	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100039	96944	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100042	100039	100041
20024	100038	776	0	0	0	0	0	0	100023	89599	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100040	100093	100039

Test 3: throughput

Count: 8

Code:

  fmov x0, v8.d[1]
  fmov x1, v8.d[1]
  fmov x2, v8.d[1]
  fmov x3, v8.d[1]
  fmov x4, v8.d[1]
  fmov x5, v8.d[1]
  fmov x6, v8.d[1]
  fmov x7, v8.d[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	311	0	0	0	0	0	0	32	25	160100	80100	80000	100	80266	500	640744	0	40180	40038	40303	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	3	0	1	1	1	5167	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	2	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40169
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	32	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	1	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	30007	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	0	0	0	1	1	1	5117	0	16	0	0	40035	81741	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	2	0	0	0	1	1	1	5117	2	32	0	0	40199	80000	80100	40105	40039	40307	40039	40303
80204	40233	310	0	0	3	3	399	264	410	80	160100	80330	80317	100	80254	580	642050	1	40236	40497	40432	30097	25	30171	80450	200	80294	200	80652	40232	40038	5	1	80201	100	99	100	80100	100	4	2	3	9	1753	2	1	1	1	5117	0	40	5	0	40035	80000	80100	40039	40233	40039	40039	40303
80204	40038	313	0	0	0	1	144	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40297	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40048	311	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	6	16	0	4	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	16	0	3	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	12	43	25	160010	80010	80000	10	80000	50	640000	1	1	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	3	5020	0	3	16	0	4	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	1	0	5020	0	3	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	127	25	160010	80010	80000	10	80000	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	3	5020	0	3	16	0	3	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	4	16	0	4	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	1	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	4	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	85	25	160010	80010	80000	10	80000	50	640000	0	1	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	1	0	43	25	160010	80010	80000	10	80000	50	640000	0	1	40019	0	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	3	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	43	25	160010	80010	80000	10	80167	50	640000	0	0	40019	0	40038	40038	29992	3	30018	80010	20	80538	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	5020	0	4	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039

FMOV (D[1] to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations