Firestorm: FMOV (D from X) measurements

Code:

  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	374	3	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	387
1004	374	3	359	0	25	1000	1000	1000	14833	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	2	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	2	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	2	359	0	25	1000	1000	1000	14200	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	359	0	25	1000	1000	1000	14060	349	374	384	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	359	0	25	1000	1000	1000	14060	349	382	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	378	375	375	375	375
1004	374	3	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	2	359	0	25	1000	1000	1000	14060	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375

Test 2: Latency 1->2 roundtrip

Code:

  fmov d0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100035	776	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100064	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96904	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	1310	1	2	16	2	2	99632	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100076	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100035	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	3	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	1310	1	2	16	2	2	99634	10000	10000	10100	100033	100033	100036	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100087	100072	100035	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	99632	10000	10000	10100	100033	100033	100033	100033	100033
20204	100034	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100073	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	100020	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100085	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	1310	1	2	16	2	3	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100035	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100278	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778182	5682794	0	100087	100094	100121	96893	3	97557	20344	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	4	3	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10001	100	10000	10000	500	4778134	5679930	0	100065	100033	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	2	2	99633	10000	10000	10100	100033	100033	100033	100033	100033

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100045	775	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	1	0	12	1270	1	16	2	1	99631	10000	0	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10006	0	6	0	0	1270	2	16	2	2	99631	10000	0	0	10000	10010	100033	100033	100033	100033	100036
20024	100032	775	0	0	0	12	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678591	0	100016	100032	100032	96915	3	97512	20010	20	10060	10000	20	10000	10000	100032	100125	1	1	20021	10	9	10	10010	10000	10	10000	0	6	0	3	1270	2	16	3	3	99631	10000	0	0	10000	10010	100034	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678702	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	2	0	0	1270	3	16	4	3	99631	10000	0	0	10000	10010	100033	100033	100033	100033	100038
20024	100032	775	0	0	0	12	0	100020	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778278	5678535	0	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	6	0	0	1270	3	16	3	1	99631	10000	0	1	10000	10010	100033	100033	100033	100033	100042
20024	100032	776	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10066	100084	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	3	16	3	2	99631	10000	0	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	1	0	12	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	2	0	3491	1270	4	16	4	3	99632	10000	0	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	12	10059	10000	50	4778278	5678535	0	100013	100032	100032	96915	3	97512	20010	20	10121	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	2	0	3	1270	8	16	3	4	99631	10000	0	0	10000	10010	100034	100034	100033	100033	100039
20024	100032	776	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	10000	0	2	0	0	1270	2	16	4	1	99631	10000	0	0	10000	10010	100033	100035	100033	100036	100080
20024	100032	775	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	100013	100061	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100034	1	1	20021	10	9	10	10010	10000	10	10006	0	76	0	3478	1288	3	16	3	3	99631	10000	0	0	10000	10010	100033	100033	100033	100033	100048

Test 3: throughput

Count: 8

Code:

  fmov d0, x8
  fmov d1, x8
  fmov d2, x8
  fmov d3, x8
  fmov d4, x8
  fmov d5, x8
  fmov d6, x8
  fmov d7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26707	207	0	0	0	0	26697	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26713	26708	26708
80204	26707	207	0	0	0	0	26695	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26711	26707	16635	6	16663	80115	200	80024	200	80024	26711	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	3	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26696	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26723	208	0	0	0	0	26694	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16639	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26704	0	25	80100	100	80000	100	80015	500	1166596	1	26686	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	1	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26692	2	25	80100	100	80000	100	80015	500	1166596	1	26682	26711	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	3	0	1	1	1	5118	0	16	0	0	26704	80000	100	26713	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26698	0	25	80100	100	80000	100	80016	500	1166596	1	26682	26707	26707	16639	6	16659	80114	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26816	0	25	80100	100	80000	100	80015	500	1166596	1	26686	26707	26707	16635	6	16659	80115	200	80024	200	80024	26712	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	27158	26708	26852

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26719	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26705	80000	10	26709	26709	26712	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26711	26711	16652	3	16688	80010	20	80000	20	80000	26708	26712	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26708	80000	10	26712	26712	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26708	80000	10	26709	26709	26711	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26711	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	3	5020	0	0	1	16	0	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26711	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	1	0	1	16	0	1	1	26705	80000	10	26709	26712	26709	26709	26712
80024	26708	207	0	0	0	26693	2	25	80010	10	80000	10	80000	50	1165994	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26705	80000	10	26712	26709	26709	26709	26709
80024	26711	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	1	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80193	20	80000	26709	26715	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	1	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26711	1	1	80021	10	9	10	10	80000	10	0	0	80000	0	0	0	5020	0	0	1	16	0	1	1	26708	80000	10	26709	26709	26709	26713	26709

FMOV (D from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations