Firestorm: FMOV (D to X) measurements

Code:

  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	12	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	71	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539
1004	538	4	1	1	0	2	50	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	4	16	4	4	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  fmov x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	775	0	0	0	0	0	0	0	0	100023	89568	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96907	6	97492	20100	200	10004	10004	200	10004	10004	100039	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	99646	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89615	25	30100	10100	10000	10000	100	10000	10000	500	4778529	5580349	0	100013	100067	100038	96909	6	97492	20100	200	10004	10004	200	10004	10004	100041	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	99646	10000	10000	10100	100039	100039	100039	100039	100040
20204	100038	776	0	0	0	0	0	387	0	0	100023	89603	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100016	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	0	0	1310	1	2	16	3	2	99640	10000	10000	10100	100039	100042	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89622	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96901	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	3	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	12	0	0	100023	89632	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100039	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89627	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100040	100039	100123	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89628	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	12	0	0	100023	89592	25	30100	10100	10000	10004	100	10000	10000	500	4778481	5580349	1	100013	100038	100038	96900	3	97499	20100	200	10000	10000	200	10000	10127	100038	100124	2	1	20201	100	99	100	10100	10000	100	0	2	10000	0	1	0	0	0	0	0	0	1328	1	2	16	2	3	99637	10000	10000	10100	100039	100039	100039	100039	100042
20204	100038	775	0	0	0	0	0	0	0	0	100023	89593	25	30100	10100	10000	10000	100	10000	10000	500	4778577	5580349	0	100013	100038	100041	96900	3	97671	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10050	2	5	0	136460	0	0	0	0	2089	1	3	16	4	4	102855	10143	10000	10100	103578	104174	103910	104049	104139
20204	103861	832	0	1	0	3	0	5676	3784	0	100023	89607	25	30100	10104	10000	10004	100	10000	10000	500	4778481	5679015	0	100015	100039	100038	96908	3	97496	20100	200	10000	10000	200	10000	10000	100038	100044	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100073	100046	100039	100042	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	776	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	12	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100040	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4781870	5606034	0	0	100017	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100067	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	2	1	99640	10000	10000	10010	100039	100042	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	1	100013	0	100038	100040	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100040	100039	100039
20024	100038	775	0	0	0	0	0	12	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	1	100013	0	100038	100038	96923	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100041	775	0	0	0	0	0	12	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100040	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100041	100039	100039	100039
20024	100038	775	0	0	0	0	0	18	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100040	100039
20024	100038	776	0	0	0	0	0	0	0	0	100023	89565	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100014	0	100039	100038	96925	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100204
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	6	0	0	1270	1	16	1	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100042	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  fmov x0, d8
  fmov x1, d8
  fmov x2, d8
  fmov x3, d8
  fmov x4, d8
  fmov x5, d8
  fmov x6, d8
  fmov x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	310	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	32	25	160100	80520	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	6	0	3	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	12	0	102	25	160100	80100	80000	100	80004	500	640024	0	40126	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	4	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	12	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	2	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	12	0	118	62	160268	80100	80000	100	80004	500	640024	0	40019	0	40105	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40104	2	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40108	40238
80204	40038	312	0	0	0	264	854	62	160100	80100	80000	100	80004	500	640024	0	40019	3	40236	40038	29976	0	6	30177	80104	200	80016	200	80016	40038	40038	4	1	80201	100	99	100	80100	100	0	0	0	40	0	0	0	1	1	1	5117	0	48	0	0	40035	80000	80100	40039	40234	40039	40039	40039
80204	40038	310	0	0	0	0	74	25	160100	80348	80000	100	80004	500	640024	0	40019	0	40038	40174	29976	0	6	29991	80358	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	2	0	34	0	0	0	1	1	1	5134	0	16	0	0	40035	80000	80100	40039	40039	40039	40307	40039
80204	40240	322	1	3	624	0	74	82	160100	80100	80082	100	80004	500	640024	0	40019	0	40038	40038	29976	0	6	30129	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	3	0	3	0	1	1	1	5117	0	16	0	0	40195	80000	80100	40332	40039	40241	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40039	310	0	64	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	3	0	5020	7	16	0	4	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	3	16	0	4	5	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	113	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	3	0	5020	4	16	0	4	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	4	16	0	2	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	2	16	0	4	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	723	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	4	16	5	6	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	4	16	0	4	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	1	0	0	5020	2	16	0	4	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	12	218	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	2	16	0	6	4	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	708	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	4	16	0	3	6	40035	80000	80010	40039	40039	40039	40039	40039

FMOV (D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations