Firestorm: FMOV (H from W) measurements

Code:

  fmov h0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	374	3	0	0	2	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	2	1	0	2	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	2	359	0	25	1000	1000	1000	14060	0	349	374	376	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	378	387	375	375
1004	374	3	1	0	2	359	3	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	2	364	2	25	1000	1000	1000	14060	1	352	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	3	359	0	25	1000	1000	1000	14121	1	349	374	379	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	2	359	0	25	1000	1000	1000	14060	1	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	2	359	0	25	1000	1000	1000	14060	1	349	374	379	198	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	388	380	375
1004	374	2	0	0	2	359	0	25	1000	1000	1000	14060	1	353	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	371	1000	375	375	375	375	375
1004	374	3	1	0	2	359	0	25	1000	1000	1000	14060	1	349	374	374	197	3	236	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	77	4	16	4	4	375	1000	375	375	375	379	375

Test 2: Latency 1->2 roundtrip

Code:

  fmov h0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100032	776	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	4	100013	100032	100032	96900	6	97486	20100	200	10004	10004	200	10004	10004	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1	1	1	1318	0	1	16	1	1	99640	10000	10000	10100	100120	100374	100116	100034	100033
20204	100032	775	0	0	0	0	0	0	0	100017	89558	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100032	100035	96900	6	97489	20100	200	10004	10004	200	10004	10004	100058	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1	1	1	1317	0	1	16	1	2	99640	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	0	100017	89555	44	30100	10100	10000	10000	100	10059	10000	500	4778134	5679930	0	0	100125	100032	100372	96894	3	97493	20223	200	10000	10000	200	10000	10000	100059	100083	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1311	1	3	17	2	2	99631	10000	10000	10100	100034	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	1	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100033	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100046	100034	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	0	0	1311	1	3	16	3	3	99631	10000	10000	10100	100033	100033	100033	100035	100033
20204	100032	775	0	0	0	0	9	0	0	100017	89558	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100032	100032	96893	3	97491	20100	200	10000	10000	200	10000	10000	100065	100033	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	48	3	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	1	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100032	100035	96893	3	97490	20100	200	10000	10000	200	10000	10000	100034	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1311	1	2	16	3	3	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100035	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100070	100035	1	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	0	0	0	0	1310	1	3	16	3	3	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	1	100017	89555	25	30100	10100	10000	10000	100	10000	10050	500	4778134	5679930	0	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100059	100032	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	1311	1	2	16	3	2	99631	10000	10000	10100	100033	100033	100034	100033	100033
20204	100032	776	0	0	0	0	0	0	1	100017	89555	25	30100	10100	10000	10000	104	10000	10000	581	4778134	5680096	0	0	100174	100127	100032	96893	3	97490	20206	200	10000	10000	200	10000	10000	100055	100065	1	1	20201	100	99	100	10100	10000	100	0	0	10008	1	0	3426	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	1	0	0	0	1	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	0	100013	100032	100033	96893	3	97490	20100	200	10000	10000	200	10000	10000	100073	100036	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	3	48	3	3	99631	10000	10000	10100	100033	100033	100135	100033	100034

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100039	775	0	0	0	0	0	0	12	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	0	100013	0	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	3	16	0	2	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	0	100013	0	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	2	16	0	4	3	99631	10000	0	10000	10010	100034	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	0	100013	0	100032	100032	96916	3	97514	20010	20	10000	10000	20	10000	10000	100032	100035	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	3	16	0	2	3	99631	10000	0	10000	10010	100033	100033	100033	100035	100033
20024	100032	775	0	0	0	1	0	0	12	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	0	100014	0	100032	100032	96916	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	3	16	0	3	2	99631	10000	0	10000	10010	100035	100033	100033	100062	100033
20024	100032	775	0	0	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	0	100013	0	100032	100036	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	3	16	0	3	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	0	100013	0	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100033	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	3	16	0	3	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5679047	1	0	100013	0	100033	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	3	16	0	3	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	0	0	100017	89557	0	25	30010	10010	10000	10000	10	10000	10000	50	4779043	5678535	0	1	100013	0	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	2	16	0	3	3	99699	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100033	775	0	1	0	0	0	0	0	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	1	100013	0	100032	100032	96918	3	97512	20010	20	10000	10066	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	3	16	0	2	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	12	0	0	100017	89555	0	25	30010	10010	10000	10000	10	10000	10000	50	4778278	5678535	0	1	100013	0	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	0	1270	0	3	16	0	3	3	99631	10000	0	10000	10010	100033	100033	100033	100033	100033

Test 3: throughput

Count: 8

Code:

  fmov h0, w8
  fmov h1, w8
  fmov h2, w8
  fmov h3, w8
  fmov h4, w8
  fmov h5, w8
  fmov h6, w8
  fmov h7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26712	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26833	26715	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26712	26708	26708	26708	26708
80204	26707	206	0	0	0	0	0	0	0	26692	29	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26718	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	2	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26713	26713	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26695	0	25	80100	100	80000	100	80014	500	1166596	26686	26707	26707	16639	6	16663	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26709	27204	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26714	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26722	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	1	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	206	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26708	26722	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	26707	26716	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	26682	26707	26707	16635	6	16659	80115	200	80024	200	80024	27304	26711	1	1	80201	100	99	100	100	80000	100	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26718	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	4	16	0	0	0	4	4	3	26715	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26712	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	3	0	5023	3	0	0	3	16	0	0	0	4	4	3	26705	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	3	16	0	0	0	3	4	3	26705	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26687	26708	26708	16652	3	16692	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	4	16	0	0	0	4	4	3	26705	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26696	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	4	16	0	0	0	4	4	3	26705	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	1	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	4	16	0	0	0	3	4	3	26705	0	80000	10	26709	26712	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	3	16	0	0	0	3	4	3	26705	0	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26697	0	25	80010	10	80000	10	80000	50	1166600	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	3	16	0	0	0	4	4	3	26705	0	80000	10	26713	26709	26712	26709	26709
80024	26708	206	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	1	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	3	16	0	0	0	4	4	3	26705	0	80000	10	26709	26712	26709	26709	26709
80024	26711	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	0	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26711	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	0	5023	3	0	0	4	16	0	0	0	4	3	3	26705	0	80000	10	26709	26709	26709	26709	26709

FMOV (H from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations