Firestorm: FMOV (H from X) measurements

Code:

  fmov h0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	374	3	0	0	359	25	1000	1000	1000	14060	1	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	359	25	1000	1000	1000	14102	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	359	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	376	375
1004	376	3	0	0	359	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	3	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	359	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	359	25	1000	1000	1000	14072	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	2	0	0	359	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	361	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	0	359	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	377	1	1	1001	1000	0	1000	0	3	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	21	359	25	1000	1000	1178	14108	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	0	1000	2	0	73	1	16	1	1	371	1000	375	375	375	375	375

Test 2: Latency 1->2 roundtrip

Code:

  fmov h0, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	1310	1	3	17	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778278	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100068	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89556	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	7	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	6	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	1	3	0	1310	1	2	16	2	2	99631	10000	10000	10100	100035	100033	100033	100033	100035
20204	100035	776	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97491	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	521	4778134	5679930	0	100013	100034	100034	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	1	0	0	1310	1	2	16	3	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	21	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	1	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	33	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	776	0	2	0	132	0	1	100017	89556	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	1310	1	3	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	100020	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5680095	0	100013	100032	100032	96893	3	97490	20100	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	24	2	2	99836	10000	10000	10100	100123	100034	100225	100033	100126

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100032	776	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	3	16	1	1	99631	10000	10000	10010	100036	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100059	100033	100033	100033	100033
20024	100032	775	0	0	0	5	1	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	2	1	99631	10000	10000	10010	100033	100033	100033	100033	100033
20024	100033	775	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678927	1	100013	100127	100032	96915	18	97724	20010	20	10242	10000	20	10000	10000	100032	100377	5	1	20021	10	9	10	10010	10000	10	4	0	10004	0	0	0	0	0	0	1288	1	16	2	1	99797	10000	10000	10010	100033	100033	100034	100033	100033
20024	100032	776	0	0	0	0	0	24	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100034	96944	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	3	0	0	1270	1	16	1	1	99631	10000	10000	10010	100035	100034	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100068	100035	100033	100033
20024	100032	776	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	0	100013	100033	100032	96915	3	97514	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	3	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	1	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	1270	1	16	1	1	99660	10000	10000	10010	100033	100033	100033	100034	100033

Test 3: throughput

Count: 8

Code:

  fmov h0, x8
  fmov h1, x8
  fmov h2, x8
  fmov h3, x8
  fmov h4, x8
  fmov h5, x8
  fmov h6, x8
  fmov h7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26709	207	0	0	0	0	0	0	26694	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16732	80114	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	2	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	26696	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26712	26707	16635	6	16726	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26711	26707	16639	6	16733	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26712
80204	26707	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26686	26707	26707	16635	6	16776	80114	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26715
80204	26707	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	0	26682	26707	26707	16639	6	16775	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	26692	2	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16728	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	3	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1168008	0	26682	26707	26707	16635	6	16786	80116	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	3	0	1	1	1	5118	0	16	0	0	26704	80000	100	26712	26708	26708	26708	26708
80204	26707	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	0	26682	26707	26711	16635	6	16659	80115	200	80024	200	80024	26716	26707	1	1	80201	100	99	100	100	80000	100	0	0	80000	1	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26857	26708	26708	26712	26708
80204	26860	207	0	0	0	0	0	0	26692	0	25	80100	100	80000	100	80015	500	1166596	0	27096	26707	26707	16635	6	16890	80115	200	80024	200	80024	27321	26707	1	1	80201	100	99	100	100	80000	100	2	0	80000	0	0	0	1	1	1	5118	0	16	0	0	27110	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	0	0	6	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26686	26707	27157	16635	6	16779	80115	200	80024	200	80024	26707	26711	1	1	80201	100	99	100	100	80000	100	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	27157	26708	26712

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26691	26708	26708	16652	3	16692	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26691	26708	26711	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26712	26709
80024	26708	206	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26690	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	60	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26726	26708	26711	16658	3	16688	80010	20	80000	20	80000	26882	26866	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26690	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26692	26708	26708	16652	3	16692	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26713	26709	26709	26709	26709
80024	26711	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26692	26711	26709	16652	3	16676	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26712	26709
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26693	26708	26709	16652	3	16691	80010	20	80000	20	80000	26711	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26708	80000	10	26709	26709	26710	26709	26709
80024	26708	207	384	26693	3	25	80010	10	80000	10	80000	50	1166750	0	1	26824	26708	26708	16657	3	16688	80188	20	80000	20	80000	26916	26858	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	1	16	1	1	26705	80000	10	26713	26709	26709	26712	26709
80024	26708	207	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26690	26708	26708	16652	3	16688	80010	20	80000	20	80000	26711	26708	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	1	16	1	1	26705	80000	10	26709	26709	26709	26709	26709

FMOV (H from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations