Firestorm: FMOV (H to W) measurements

Code:

  fmov w0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	64	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	5	0	0	128	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	1	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	108	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  fmov w0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	3	16	2	2	99638	10000	10000	10100	101183	101424	100549	100254	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4780017	5580850	0	100013	100038	100041	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100074	100039
20204	100038	775	0	0	0	0	0	528	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4780449	5580517	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	12	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4780689	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100040	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89562	25	30100	10100	10000	10000	100	10000	10000	500	4779921	5580684	0	100013	100038	100039	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	590	4779777	5580520	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3508	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	777	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4779777	5580349	0	100014	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	14	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	9	0	0	100065	89561	25	30148	10127	10006	10000	119	10000	10050	500	4784106	5580349	0	100014	100207	100041	96957	3	97627	20452	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	6	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100039	776	0	0	0	0	0	0	0	0	100026	89561	25	30100	10100	10000	10000	100	10000	10000	500	4780401	5580406	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100042	100039	100042	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89562	25	30100	10100	10000	10000	100	10000	10000	500	4778769	5580349	0	100016	100128	100038	96993	15	97496	20329	200	10000	10000	200	10000	10000	100038	100213	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch ret (8f)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	775	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10008	10008	10	10000	10000	50	4778481	5578954	0	100013	0	100039	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10008	0	0	0	2	1343	2	16	2	2	99691	10000	10000	10010	100372	100317	100286	100316	100265
20024	100346	777	0	0	0	1	0	0	0	100501	89561	25	30020	10013	10000	10000	10	10000	10050	61	4778481	5578954	0	100013	0	100038	100038	96922	3	97519	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	2	1	99637	10000	10000	10010	100039	100039	100039	100040	100039
20024	100038	776	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579116	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10061	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	2	16	3	2	99637	10000	10000	10010	100039	100129	100039	100039	100131
20024	100038	775	1	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100016	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778577	5578954	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	2	2	99637	10000	10000	10010	100040	100039	100039	100040	100042
20024	100038	775	0	0	0	0	12	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100085	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	2	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	12	0	0	100023	89563	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100014	0	100038	100038	96925	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	2	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100041
20024	100038	775	0	0	0	0	6	0	0	100023	89568	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	2	99639	10000	10000	10010	100039	100039	100039	100039	100043
20024	100038	775	0	0	0	0	0	0	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100070	100038	1	1	20021	10	0	9	10	10010	10000	10	0	0	10000	8	2	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  fmov w0, h8
  fmov w1, h8
  fmov w2, h8
  fmov w3, h8
  fmov w4, h8
  fmov w5, h8
  fmov w6, h8
  fmov w7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40054	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	6	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	718	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	9	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40106
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	325	1	1	0	99	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	96	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	12	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	105	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	147	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	1	1	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	9	1	1	1	5117	1	16	1	1	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40047	310	0	0	0	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	3	30018	80010	20	80000	20	80088	40038	40238	3	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	2	16	2	3	3	40035	80000	80010	40039	40039	40039	40039	40168
80024	40038	314	0	0	0	0	0	0	0	0	0	0	708	62	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	4	0	0	0	0	0	0	0	5020	3	16	1	3	3	40035	80000	80010	40107	40039	40039	40039	40106
80024	40038	313	0	0	0	0	0	0	0	0	12	0	299	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	0	0	5020	2	24	1	2	2	40089	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	7	1	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40169	29992	0	3	30018	80010	20	80000	20	80000	40038	40104	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	3	0	5020	2	16	0	2	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	1	0	0	0	0	0	1422	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	30023	0	3	30018	80010	20	80000	20	80630	40038	40038	2	1	80021	10	9	10	80010	10	0	2	0	0	0	0	108	4	5020	2	24	1	3	2	40088	80000	80010	40039	40039	40039	40105	40039
80024	40038	311	0	0	0	0	0	0	7	0	9	0	1092	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	4	16	2	2	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	0	15	0	951	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	30024	0	3	30240	80010	20	80629	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	3	0	5020	2	16	2	3	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	313	0	0	0	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	3	30064	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5038	2	16	1	2	7	40255	80079	80010	40039	40039	40039	40039	40104
80024	40038	310	0	0	0	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80169	50	641898	0	0	40019	40038	40038	29992	0	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	2	0	0	5020	2	16	2	2	3	40035	80000	80010	40039	40039	40104	40039	40039
80024	40038	311	0	0	0	0	0	0	0	1	9	0	43	25	160010	80010	80000	10	80000	50	640000	0	0	40019	40038	40038	29992	0	8	30341	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	1253	0	5037	3	16	2	3	3	40090	80000	80010	40039	40039	40039	40039	40039

FMOV (H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations