Firestorm: FMOV (H to X) measurements

Code:

  fmov x0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	85	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	5	12	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	138	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	3	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  fmov x0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	d8	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	0	90	0	0	100025	89606	25	30100	10100	10000	10000	121	10000	10000	531	4778625	5580349	0	100013	0	100038	100038	96907	6	97492	20100	202	10004	10004	200	10004	10004	100038	100041	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	1	1	1317	0	2	16	0	1	1	99646	10000	10000	10100	100042	100039	100039	100039	100039
20204	100038	776	1	0	0	0	0	0	0	1	100023	89561	25	30100	10100	10000	10002	100	10000	10000	561	4778481	5580349	0	100013	0	100133	100038	96997	6	97492	20100	200	10004	10004	202	10004	10004	100040	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1	1	1	1317	0	1	16	0	1	1	99646	10022	10000	10100	100039	100039	100039	100039	100131
20204	100044	775	0	0	0	0	0	12	0	0	100112	89562	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100014	0	100039	100038	96907	6	97493	20100	200	10004	10004	200	10004	10004	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	2	1	1	1	1317	0	1	16	0	1	1	99739	10000	10000	10100	100121	100129	100039	100127	100041
20204	100133	775	1	0	0	0	0	12	0	0	100189	89611	63	30137	10114	10000	10004	100	10000	10000	500	4778481	5580349	0	100013	0	100038	100038	96907	6	97492	20100	200	10004	10247	200	10067	10004	100040	100038	1	1	20201	100	99	100	10100	10000	100	0	2	10000	0	0	0	0	0	1	1	1	1317	0	1	16	0	1	1	99646	10000	10000	10100	100039	100039	100039	100041	100039
20204	100038	776	0	0	0	0	0	0	0	0	100023	89598	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580520	0	100015	0	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100041	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	3	0	0	0	0	1310	1	2	25	0	2	3	99637	10000	10000	10100	100039	100039	100041	100121	100122
20204	100038	776	0	0	0	0	0	6	0	0	100202	89564	25	30119	10125	10000	10004	100	10238	10000	500	4778481	5583988	0	100013	0	100055	100038	96900	3	97496	20668	200	10000	10000	200	10000	10000	100040	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	2	0	0	0	0	0	0	1328	1	2	16	0	2	2	99640	10000	10000	10100	100136	100039	100040	100041	100039
20204	100041	776	0	0	0	0	0	24	0	0	100023	89561	25	30100	10116	10002	10000	123	10411	10000	500	4778481	5580349	0	100013	0	100040	100041	96900	7	97499	20100	200	10000	10000	200	10061	10000	100551	100040	6	1	20201	100	99	100	10100	10000	100	0	0	10000	0	2	0	0	0	0	0	0	1310	1	2	16	0	2	2	99637	10003	10000	10100	100531	100125	100039	100039	100039
20204	100038	776	1	0	0	0	0	42	0	0	100339	89561	25	30100	10100	10000	10002	100	10000	10000	500	4778481	5580349	0	100013	0	100039	100430	97187	3	97496	20453	200	10000	10000	202	10060	10000	100309	100038	2	1	20201	100	99	100	10100	10000	100	4	2	10002	0	2	0	3495	0	0	0	0	1310	1	2	16	0	2	2	99640	10000	10000	10100	100039	100039	100118	100088	100039
20204	100039	775	0	0	0	0	1	0	0	0	100025	89626	25	30100	10100	10000	10000	100	10000	10000	596	4779109	5580349	0	100013	0	100038	100038	96902	3	97498	20322	200	10000	10124	202	10061	10000	100048	100041	1	1	20201	100	99	100	10100	10000	100	0	0	10005	0	0	2	0	0	0	0	0	1310	1	2	16	0	2	2	99638	10033	10000	10100	100040	100039	100039	100040	100039
20204	100124	776	0	0	0	0	0	171	0	0	100023	89561	42	30127	10100	10000	10000	100	10000	10000	500	4780977	5580349	0	100013	0	100038	100039	96900	10	97498	20100	200	10000	10000	200	10000	10000	100038	100134	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	3	0	3	0	0	0	0	1310	1	3	25	0	2	3	99640	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	775	0	0	0	0	21	0	0	100023	89561	25	30010	10010	10000	10002	10	10000	10000	50	4778529	5582990	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	2	0	0	0	0	1270	11	16	3	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	1	1	0	0	0	0	0	100023	89562	25	30010	10010	10000	10002	10	10000	10000	50	4779345	5579064	1	100013	3	100083	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	3	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100042	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4781361	5579788	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100040	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4781937	5580059	0	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	2	1	99637	10000	10000	10010	100040	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89564	25	30010	10010	10000	10000	10	10000	10000	50	4782465	5611905	1	100162	0	100039	100038	96922	3	97518	20010	20	10000	10121	20	10000	10000	100039	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	2	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4781697	5581625	1	100013	0	100038	100038	96922	3	97518	20010	20	10066	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	2	1	99640	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	100023	89563	25	30010	10010	10000	10000	10	10000	10000	50	4780113	5579062	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89563	25	30010	10010	10000	10000	10	10000	10000	50	4779969	5579009	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	2	16	2	1	99637	10000	10000	10010	100039	100039	100042	100039	100041
20024	100038	775	0	0	0	0	0	0	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4780881	5578954	0	100013	0	100038	100046	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	1	2	99640	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10004	11	10000	10000	50	4789877	5578954	1	100013	0	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	2	16	1	1	99637	10000	10000	10010	100039	100039	100041	100039	100039

Test 3: throughput

Count: 8

Code:

  fmov x0, h8
  fmov x1, h8
  fmov x2, h8
  fmov x3, h8
  fmov x4, h8
  fmov x5, h8
  fmov x6, h8
  fmov x7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	312	0	1	4	144	0	32	25	160576	80100	80000	102	80004	500	642036	1	40181	40038	40238	29976	20	30130	80440	200	80390	204	80293	40238	40038	4	1	80201	100	99	100	80100	100	2	2	0	1	1673	2	1	1	1	5168	1	40	1	40200	80000	80100	40039	40173	40233	40039	40039
80204	40038	311	0	0	0	144	176	419	25	160276	80100	80000	100	80004	500	642058	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40237	40038	1	1	80201	100	99	100	80100	100	0	2	0	1	0	2	1	1	1	5117	0	16	0	40035	80000	80100	40039	40232	40039	40236	40039
80204	40232	310	0	0	2	408	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	57	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40236	40039
80204	40038	310	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	130	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40304	40039	40039
80204	40038	310	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	l2 tlb miss instruction (0a)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	40048	310	0	0	0	0	0	0	518	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	27	0	5020	0	13	16	1	0	0	10	16	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	16	16	0	0	0	17	14	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	16	16	0	0	0	16	12	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	1	1	0	0	0	0	92	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	3	0	5021	1	17	16	0	0	1	17	17	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	18	16	0	0	0	18	17	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	15	16	0	0	1	15	15	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	17	16	0	1	1	17	14	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	0	0	5021	1	17	16	0	0	1	17	17	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	1	0	0	12	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5021	1	17	16	0	0	1	15	18	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	1	1	0	0	0	0	91	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	0	0	5021	1	14	16	0	0	0	16	8	40035	80000	0	80010	40039	40039	40039	40039	40039

FMOV (H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations