Firestorm: FMOV (S from W) measurements

Code:

  fmov s0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	374	3	0	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	381	375	376	375	375
1004	374	2	0	359	0	25	1000	1000	1000	14060	1	349	374	374	241	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	379	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	2	0	359	0	25	1000	1000	1000	14060	1	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	1	3	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	1	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	378	375	375
1004	377	2	0	359	0	25	1000	1000	1000	14418	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	1	439	377	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	7	3	73	1	16	1	1	371	1000	375	375	375	375	375
1004	374	3	0	359	0	25	1000	1000	1000	14060	0	349	374	374	197	3	232	1000	1000	1000	374	374	1	1	1001	1000	1000	0	0	73	1	16	1	1	371	1000	375	375	375	375	375

Test 2: Latency 1->2 roundtrip

Code:

  fmov s0, w0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	7a	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100032	775	0	0	0	0	0	99	0	100020	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	1	100013	100032	100032	96900	6	97486	20100	0	200	10004	10004	200	10004	10004	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	1	1	1	1317	0	2	16	1	1	99640	10000	10000	10100	100035	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679988	1	100013	100032	100032	96900	6	97486	20100	0	200	10004	10004	200	10004	10004	100034	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	1	1	1	1317	0	1	16	1	1	99640	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778230	5679930	1	100016	100032	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	6	0	0	0	1310	1	1	16	2	2	99631	10000	10000	10100	100034	100033	100033	100033	100033
20204	100032	776	0	0	0	0	0	0	0	100019	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	1	100013	100032	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100070	100033	100033	100033	100036
20204	100033	775	0	0	0	0	0	0	88	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679988	1	100013	100032	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100037
20204	100032	775	0	0	0	0	0	0	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	1	100013	100032	100033	96895	3	97490	20100	0	200	10000	10000	200	10000	10000	100034	100035	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100035	100033	100033
20204	100032	775	0	0	0	0	0	12	0	100017	89555	25	30100	10100	10000	10000	100	10000	10050	500	4778134	5679930	0	100013	100032	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	12	0	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	1	100013	100032	100032	96893	3	97490	20215	0	200	10000	10000	200	10000	10000	100035	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	0	0	1310	1	2	16	2	2	99711	10017	10000	10100	100033	100033	100033	100033	100033
20204	100032	775	0	0	0	0	0	0	108	100017	89555	25	30100	10100	10000	10000	100	10000	10000	500	4778134	5679930	0	100013	100033	100032	96893	3	97490	20100	0	200	10000	10000	200	10000	10000	100032	100032	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	0	0	1310	1	2	16	2	2	99631	10000	10000	10100	100033	100033	100033	100033	100033

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100032	775	0	0	0	0	0	0	0	100017	89557	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10183	10000	100035	100032	1	1	20021	10	9	10	10010	10000	10	0	10008	9	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100082	100074	100033	100033	100033
20024	100032	775	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100014	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100048	100034	100037	100033	100033
20024	100032	776	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100013	100033	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100034	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	1	16	2	1	99631	10005	10000	10010	100064	100033	100033	100033	100033
20024	100033	775	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778182	5678535	100013	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100034	100034	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	100019	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100014	100032	100032	96915	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99634	10009	10000	10010	100403	100365	100390	100391	100388
20024	100380	778	1	0	4	4	528	352	0	100367	89556	25	30010	10010	10003	10008	11	10400	10200	66	4789474	5605321	100267	100376	100371	97114	17	97766	20445	20	10241	10301	20	10304	10241	100376	100412	6	1	20021	10	9	10	10010	10000	10	4	10010	0	2	13595	0	0	1270	1	16	1	2	99634	10000	10000	10010	100105	100039	100033	100033	100033
20024	100038	775	0	0	0	0	0	0	0	100017	89557	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100135	100032	100032	96915	3	97517	20225	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	32	1	1	99631	10007	10000	10010	100033	100033	100033	100033	100033
20024	100032	776	0	0	0	0	0	0	0	100017	89556	25	30010	10016	10000	10000	10	10000	10000	50	4778134	5678535	100013	100033	100209	96915	3	97512	20010	20	10000	10000	20	10000	10060	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100033	100033	100033	100033
20024	100032	775	0	0	0	0	12	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10100	50	4778134	5678535	100013	100032	100032	96917	3	97512	20010	20	10000	10000	20	10000	10000	100032	100032	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	1	25	1	1	99631	10000	10000	10010	100033	100034	100033	100033	100036
20024	100032	776	0	0	0	0	0	0	0	100017	89555	25	30010	10010	10000	10000	10	10000	10000	50	4778134	5678535	100013	100032	100032	96915	3	97629	20010	20	10000	10000	20	10000	10000	100032	100035	2	1	20021	10	9	10	10010	10000	10	0	10000	1	0	153	0	0	1270	1	16	1	1	99631	10000	10000	10010	100033	100033	100033	100033	100037

Test 3: throughput

Count: 8

Code:

  fmov s0, w8
  fmov s1, w8
  fmov s2, w8
  fmov s3, w8
  fmov s4, w8
  fmov s5, w8
  fmov s6, w8
  fmov s7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26707	207	0	0	426	0	26692	0	25	80100	100	80000	100	80015	500	1164038	1	26682	26707	26707	16639	6	16664	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26712	26708	26708	26708
80204	26707	207	0	0	18	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26686	26707	26707	16635	6	16660	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	189	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16751	80115	200	80024	200	80024	26707	26711	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	369	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16659	80114	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	1	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	360	0	26692	0	25	80100	100	80000	100	80014	500	1166596	1	26686	26707	26707	16639	6	16777	80116	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	102	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26710	16635	6	16659	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26707	207	0	0	381	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26687	26707	26707	16635	6	16765	80114	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26712	26708	26708	26708
80204	26707	207	0	0	375	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16808	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708
80204	26711	207	0	0	285	0	26692	0	25	80100	100	80000	100	80014	500	1166596	0	26682	26707	26711	16635	6	16744	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	1	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26712	26708	26708	26708	26708
80204	26707	207	0	0	369	0	26692	0	25	80100	100	80000	100	80015	500	1166596	1	26682	26707	26707	16635	6	16778	80115	200	80024	200	80024	26707	26707	1	1	80201	100	99	100	100	80000	100	0	0	0	80000	0	0	0	1	1	1	5118	0	16	0	0	26704	80000	100	26708	26708	26708	26708	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26694	26708	26712	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	14	16	11	12	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26694	26712	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	10	16	10	9	26705	80000	10	26709	26709	26709	26709	26712
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	3	5020	11	16	11	12	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	206	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26711	26708	1	1	80021	10	9	10	10	80000	10	80000	1	3	5020	10	16	12	10	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16692	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	10	16	11	11	26705	80000	10	26709	26709	26709	26712	26709
80024	26708	207	0	12	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	10	16	11	8	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	12	16	11	12	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26708	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	11	16	10	8	26705	80000	10	26709	26709	26709	26709	26709
80024	26708	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26683	26708	26708	16652	3	16688	80010	20	80000	20	80000	26708	26711	1	1	80021	10	9	10	10	80000	10	80000	0	0	5020	11	16	11	7	26705	80000	10	26709	26709	26709	26709	26709
80024	26711	207	0	0	0	26693	0	25	80010	10	80000	10	80000	50	1166750	0	1	26762	26721	26708	16654	3	16688	80010	20	80000	20	80000	26708	26711	1	1	80021	10	9	10	10	80000	10	80000	1	0	5020	13	16	7	14	26705	80000	10	26709	26712	26709	26713	26709

FMOV (S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations