Firestorm: FMOV (S to W) measurements

Code:

  fmov w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	1	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	3	16	3	3	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	1	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	3	16	3	3	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  fmov w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	1	100029	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	4	0	10000	0	0	0	0	1310	1	2	16	2	3	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	100024	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97499	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	100056	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100039	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100042	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	100024	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100039	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	3	3	99637	10000	10000	10100	100041	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	100046	89561	25	30100	10100	10000	10000	100	10000	10000	626	4778481	5580349	100042	100038	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	4	17	2	4	99637	10025	10000	10100	100040	100039	100039	100039	100040
20204	100038	775	0	0	0	0	0	100370	89561	25	30100	10100	10000	10000	125	10000	10000	626	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	1312	1	2	16	2	3	99640	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	100027	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	3	17	4	3	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	100029	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	100045	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580404	100013	100041	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100210	100044	100119	100208	100039
20204	100038	776	0	0	0	0	0	100153	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	99637	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100039	776	0	0	0	216	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96925	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	546	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10066	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	453	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579062	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100040	775	0	0	0	48	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	54	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	3	0	1270	1	16	1	1	99696	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	279	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100042	100039	100039	100042
20024	100067	776	0	0	0	567	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100015	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100040
20024	100038	776	0	0	0	54	0	100023	89565	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5628056	1	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	258	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96927	3	97518	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1421	1	49	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	267	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100039	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	1270	1	16	1	2	99637	10000	10000	10010	100039	100039	100040	100039	100039

Test 3: throughput

Count: 8

Code:

  fmov w0, s8
  fmov w1, s8
  fmov w2, s8
  fmov w3, s8
  fmov w4, s8
  fmov w5, s8
  fmov w6, s8
  fmov w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40054	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	79	3	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	74	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	6	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	3	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	12	0	102	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	12	0	222	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	3	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	2281	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	3	0	74	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40104	40039
80204	40038	310	0	0	0	0	12	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	3	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	40047	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	3	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	16	0	2	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80250	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	2	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40234	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40233	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	3	0	5020	0	1	16	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	1	24	0	1	1	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	1708	0	5020	0	1	16	0	1	2	40357	80000	0	80010	40229	40231	40039	40039	40236
80024	40038	312	0	0	0	0	0	546	0	43	62	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	18	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	0	0	0	5020	0	1	16	0	1	4	40035	80000	0	80010	40039	40039	40039	40039	40039

FMOV (S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations