Firestorm: FMOV (register, D) measurements

Code:

  fmov d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	3	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	17	0	0	132	104	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	18	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	3	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	1	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	3	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1914	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	16	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	17	0	0	69	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1170	2037	2037	1	1	1001	1000	0	0	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	17	0	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	82	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1574	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	2035	73	16	0	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	12	124	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	73	16	0	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  fmov d0, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	161	0	0	0	0	36	0	0	82	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	21	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	15	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	160	0	0	0	0	417	0	0	103	19686	25	10100	107	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	12	0	0	97	19686	25	10100	100	10000	100	10152	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	0	0	0	82	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	160	0	0	0	0	27	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	24	0	0	89	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	12	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	12	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18421	3	18745	10125	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	161	0	0	0	0	0	0	21	0	82	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18456	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	640	10	16	5	6	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	1	0	0	0	582	0	82	19686	25	10010	10	10000	10	10152	50	2847521	0	20018	20037	20037	18447	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	640	8	24	8	8	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	3	0	82	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	2	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	640	8	16	11	5	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	27	0	294	19686	25	10010	10	10000	10	10000	61	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	8	16	7	7	19786	0	0	10000	10	20038	20038	20038	20086	20038
10024	20037	161	0	0	0	0	0	0	3	0	82	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	640	6	16	8	8	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	12	0	124	19686	25	10022	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	640	6	16	8	5	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	160	0	0	0	0	0	0	21	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	7	6	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	1	0	0	0	0	3	0	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	640	7	16	8	8	19786	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	12	0	124	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	3	640	4	16	6	6	20034	0	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	3	0	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	6	6	19786	0	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  fmov d0, d8
  fmov d1, d8
  fmov d2, d8
  fmov d3, d8
  fmov d4, d8
  fmov d5, d8
  fmov d6, d8
  fmov d7, d8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20061	155	0	0	0	0	9	0	71	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	9	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20090	20039	20039	20095	20039
80204	20039	155	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	3	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	57	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	9	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20193	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	1	0	3	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20182	20112	20106	20039
80204	20038	156	0	0	0	0	12	0	50	25	80108	100	80008	100	80020	500	640132	1	20056	20038	20088	9977	6	10013	80120	200	80032	200	80128	20038	20038	2	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	1	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	9	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	1	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	12	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	465	2	1	1	1	5135	16	0	0	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	0	191	25	80108	100	80008	100	80020	500	640132	1	20023	20091	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	16	0	0	20035	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	161	0	0	0	0	0	12	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20089	20038	1	1	80021	10	9	10	10	80000	10	0	5	0	6	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	6	88	0	39	25	80010	10	80000	10	80000	50	640772	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	48	0	0	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	162	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	0	3	0	5020	0	3	16	4	4	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	160	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	6	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80107	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	0	0	0	10015	1	4	13	2	1	40032	11	80000	10	40035	40035	40035	40107	40035
80024	40034	466	0	0	0	0	0	0	0	0	68	25	80010	10	80092	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	48	0	3	0	5020	0	3	16	3	3	20035	0	80000	10	20090	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	0	81	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	1	0	0	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	3	0	0	0	5020	0	3	16	3	3	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	132	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20089	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	5020	0	3	16	3	4	20035	0	80000	10	20039	20039	20039	20039	20039

FMOV (register, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations