Firestorm: FMOV (register, H) measurements

Code:

  fmov h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	4	3	73	4	16	3	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	6	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	103	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	5	16	5	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1686	25	1000	1000	1152	265785	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	3	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	3	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	91	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	105	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	5	16	5	4	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	4	16	4	4	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  fmov h0, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	161	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	2	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10000	20037	20037	5	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	0	0	0	117	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18424	0	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20229
10204	20371	161	0	0	0	0	0	0	0	99	19686	25	10100	100	10000	113	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	113	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10167	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1095	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	158	0	0	0	0	0	12	0	129	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	0	3	18762	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	24	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	0	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	15	10000	100	20038	20087	20085	20087	20038
10204	20037	156	0	1	1	0	0	0	0	631	19631	25	10100	100	10000	100	10000	743	2847521	20018	20037	20037	18421	0	3	18745	10100	220	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	4	1981	0	710	1	16	1	1	20007	0	10000	100	20038	20038	20086	20085	20087
10204	20084	156	0	0	0	1	1	12	88	578	19686	25	10100	100	10000	100	10000	500	2847521	20018	20102	20037	18423	0	3	18745	10256	200	10000	208	10000	20086	20084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	161	0	0	42	0	103	19686	45	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	1	16	1	1	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	61	19686	25	10010	10	10012	10	10000	50	2847521	20234	20132	20083	18447	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1990	0	640	1	16	1	1	19786	0	10000	10	20038	20038	20038	20038	20084
10024	20037	161	1	0	18	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18447	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	1975	0	640	0	24	1	1	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	61	19686	25	10010	10	10000	11	10000	50	2847521	20018	20037	20084	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	661	1	16	1	1	19786	0	10000	10	20038	20038	20038	20086	20038
10024	20037	161	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20054	20037	20037	18443	3	18767	10010	20	10000	20	10170	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	1	16	1	1	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	21	88	346	19686	25	10010	10	10000	12	10000	50	2847521	20018	20037	20085	18443	8	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	1	16	1	1	19786	0	10000	10	20038	20038	20085	20038	20038
10024	20037	161	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20083	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	1	16	1	1	19786	0	10000	10	20038	20038	20038	20038	20086
10024	20037	160	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	1	16	1	1	19786	2	10000	10	20086	20038	20038	20038	20038
10024	20037	161	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	1	24	1	1	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	160	0	0	0	0	61	19686	25	10010	12	10000	10	10000	50	2847521	20018	20037	20037	18447	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	640	1	16	2	1	19786	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  fmov h0, h8
  fmov h1, h8
  fmov h2, h8
  fmov h3, h8
  fmov h4, h8
  fmov h5, h8
  fmov h6, h8
  fmov h7, h8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	1e	3f	43	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20061	155	0	0	0	30	29	0	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	12	29	0	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	12	71	0	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	69	29	0	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	36	29	0	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	291	71	0	25	80108	100	80008	100	80020	500	640132	0	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	1	1	1	5118	0	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	21	64	0	26	80116	100	80016	100	80028	500	640196	0	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	2	2	2	2	5129	1	0	2	23	2	2	20045	0	80000	100	20049	20050	20050	20049	20049
80204	20048	156	0	0	0	189	64	0	26	80116	100	80016	100	80028	500	640196	0	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	2	2	2	5128	1	0	2	23	2	2	20046	0	80000	100	20049	20049	20050	20050	20049
80204	20048	156	0	0	0	0	64	0	26	80116	100	80016	100	80028	500	640196	0	20028	20049	20049	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	2	2	2	5128	1	0	2	23	2	2	20046	0	80000	100	20050	20049	20049	20050	20050
80204	20048	155	0	0	0	12	64	0	27	80116	100	80016	100	80028	500	640196	0	20028	20048	20048	9976	10	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	1	0	0	2	2	2	5129	1	0	2	23	2	2	20045	0	80000	100	20050	20049	20049	20050	20049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	161	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	5020	0	3	16	3	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	1665	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	3	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	3	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	1	0	3	0	5020	0	3	16	3	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	1320	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	3	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	12	0	258	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	1	0	0	0	5020	0	3	16	3	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	12	0	185	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	3	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	160	0	0	0	0	0	0	0	81	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	2	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	123	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	3	2	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	177	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	3	16	3	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640768	20019	20038	20038	9996	3	10018	80010	20	80000	20	80096	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	5020	0	2	16	2	3	20035	80000	10	20039	20039	20039	20039	20039

FMOV (register, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations