Firestorm: FMOV (vector, immediate, 2D) measurements

Code:

  fmov v0.2d, #1.0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	288	2	9	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	0	0	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	0	16	0	0	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	3	73	0	16	0	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	0	16	0	0	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	0	16	1	0	285	1000	289	289	289	289	289
1004	288	2	0	61	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	3	73	0	16	1	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	1	16	0	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	0	16	0	1	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	3	73	0	16	0	0	285	1000	289	289	289	289	289
1004	288	2	0	40	25	1000	1000	1000	7000	269	288	288	123	3	146	1000	1000	288	288	1	1	1001	1000	0	0	73	0	16	1	0	285	1000	289	289	289	289	289

Count: 8

Code:

  fmov v0.2d, #1.0
  fmov v1.2d, #1.0
  fmov v2.2d, #1.0
  fmov v3.2d, #1.0
  fmov v4.2d, #1.0
  fmov v5.2d, #1.0
  fmov v6.2d, #1.0
  fmov v7.2d, #1.0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20110	161	1	1	0	0	63	0	1	180	0	25	80207	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5128	4	16	4	3	20073	0	80000	100	20345	20039	20039	20039	20039
80204	20038	161	1	1	0	0	9	0	1	272	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	5112	4	16	3	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	1	1	0	0	0	0	1	199	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	5112	3	16	4	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	1	1	0	0	3	0	1	126	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	5112	4	16	3	4	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	1	1	0	0	27	0	1	90	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5112	4	16	3	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	1	1	0	0	18	0	1	48	0	25	80100	124	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	5112	3	16	4	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	157	1	1	0	0	36	0	1	69	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	3	0	5112	3	16	3	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	2	1	0	0	30	0	1	48	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	5112	3	16	4	4	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	1	1	0	0	30	0	1	48	0	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	1	0	0	5112	3	16	3	3	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	1	1	0	0	0	108	1	48	20022	25	80100	100	80000	100	80000	500	560000	20019	20038	20038	9973	3	9996	80100	200	80000	200	20038	20038	1	1	80201	100	99	100	100	80000	100	0	2	3	0	5112	3	16	4	3	20035	0	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	b5	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20047	161	0	0	0	0	99	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	0	0	0	5020	0	18	16	35	35	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	48	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	0	5020	0	33	16	35	32	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	18	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	17	16	35	16	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	81	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	33	16	34	17	20073	0	80000	10	20039	20039	20091	20039	20039
80024	20038	161	0	0	0	0	12	0	0	81	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	34	16	16	38	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	123	25	80010	12	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	3	0	0	5020	0	16	16	36	35	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	0	40	16	16	37	20035	0	80000	10	20042	20088	20039	20039	20039
80024	20038	161	0	0	0	0	12	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	476	0	0	5020	0	17	16	17	41	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	12	0	0	39	25	80010	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80097	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	3	0	0	5020	0	35	16	41	39	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	12	0	0	39	25	80105	10	80000	10	80000	50	560000	20019	0	20038	20038	9996	3	10018	80010	20	80000	20	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	1	3	0	0	5020	0	36	16	34	33	20035	0	80000	10	20039	20039	20039	20039	20039

FMOV (vector, immediate, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations