Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMOV (vector, immediate, 2S)

Test 1: uops

Code:

  fmov v0.2s, #1.0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)e0? simd retires (ee)f5f6f7f8fd
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110001730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289
100428824025100010001000700026928828812331461000100028828811100110000730162851000289289289289289

Test 2: throughput

Count: 8

Code:

  fmov v0.2s, #1.0
  fmov v1.2s, #1.0
  fmov v2.2s, #1.0
  fmov v3.2s, #1.0
  fmov v4.2s, #1.0
  fmov v5.2s, #1.0
  fmov v6.2s, #1.0
  fmov v7.2s, #1.0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150040258010010080000100800005005600001200192003820038997339996801002008000020020038200381180201100991001008000010000351101161120035800001002003920039200392003920039
80204200381503640258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010007651101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010020051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010000051101162120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600001200192003820038997339996801002008000020020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010000051101162120035800001002003920039200392003920039
80204200381500325258010010080000100800005005600000200192003820038997339996801002008000020020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600001200192003820038997339996801002008000020020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005005600001200192003820038997339996801002008000020020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815030040258010010080000100800005005600001200192003820038997339996801002008000020020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471550000392580010108000010800005056000012001920038200389996310018800102080000202003820038118002110910108000010005020316222003580000102003920039200392003920039
8002420038155003301232580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010105020216222003580000102003920039200392003920039
80024200381600000812580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005056216332003580000102003920039200392003920039
80024200381610000392580010108000010800005056000012001920038200389996310018800102080000202003820038118002110910108000010005020316332003580000102003920039200392003920039
80024200381610000392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020316222003580000102003920039200392003920039
80024200381610000392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010105020316332003580000102003920039200392003920039
80024200381610000392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010035020216332003580000102003920039200392003920039
800242003816100001232580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020316222003580000102003920039200392003920039
80024200381610000392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020316222003580000102003920039200392003920039
80024200381600000392580010108000010800005056000002001920038200389996310018800102080000202003820038118002110910108000010005020316222003580000102003920039200392003920039