Firestorm: FMSUB (scalar, D) measurements

Code:

  fmsub d0, d0, d1, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	2	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	9	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	66	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  fmsub d0, d0, d1, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	21	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	3	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	18	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	363	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39553	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	57	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	366	1	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	6	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	6	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40085	40038	40038	40038
10204	40037	300	0	0	0	18	0	61	39407	25	10110	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	9	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	9	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	af	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	15	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	21	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	2	1	10021	10	9	10	10	10000	10	0	0	1	6	0	0	0	640	2	32	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	8	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	408	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	423	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	489	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	540	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	22	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	670	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	516	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	4	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	27	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10160	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	1	61	39407	25	10010	12	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40224	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	12	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  fmsub d0, d1, d0, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	33	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	5	2	12	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	18	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	27	0	346	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	712	1	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	6	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	30	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	33	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	27	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	36	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	0	40018	40037	40037	38119	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	36	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	30	0	61	39407	25	10100	100	10000	100	10000	623	5706908	0	5	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	6	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	87	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	49	3	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	3	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	6	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	668	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	60	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38146	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10157	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->4

Code:

  fmsub d0, d1, d2, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	3	0	0	3	2	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	3	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	0	536	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	202	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	3	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	12	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	0	39473	10000	10	40038	40038	40038	40038	40038
10024	40084	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	103	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40078	40038	40038

Test 5: throughput

Count: 8

Code:

  fmsub d0, d8, d9, d10
  fmsub d1, d8, d9, d10
  fmsub d2, d8, d9, d10
  fmsub d3, d8, d9, d10
  fmsub d4, d8, d9, d10
  fmsub d5, d8, d9, d10
  fmsub d6, d8, d9, d10
  fmsub d7, d8, d9, d10

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20060	151	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20104	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	34	0	0	5110	2	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	70	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	20021	20040	20040	9973	3	9998	80100	200	80000	200	240000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	150	0	136	25	80010	10	80000	10	80000	50	640000	0	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	6	16	7	7	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	151	0	41	25	80010	10	80000	10	80000	50	640000	0	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	6	16	6	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	5	16	8	8	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	230	25	80010	10	80000	10	80000	50	640000	0	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	5	16	8	8	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	706	25	80010	10	80000	10	80000	50	640000	0	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	6	16	6	5	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	42	0	5020	7	16	8	8	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	7	16	7	7	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	1	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	7	16	7	7	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	240000	20040	20040	1	1	80021	10	9	10	10	80000	10	1	0	0	5020	6	16	5	6	20037	80000	10	20041	20041	20041	20041	20041

FMSUB (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations