Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FMULX (by element, 2S)

Test 1: uops

Code:

  fmulx v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03081e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
10044037300082340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037310061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
100440373100316340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300082340725100010001000531908140184037403732583389510001000200040374037111001100073135113473100040384038403840384038
10044037300061340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038
10044037300961340725100010001000531908140184037403732583389510001000200040374037111001100073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmulx v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)030b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1020440037300000006139407251010010010000100100005005706908140018400374003738115638740101002001000820020016400374003711102011009910010010000100100011171701600394890100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738115638740101002001000820020016400374003711102011009910010010000100000011171701600394900100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738115638741101002001000820020016400374003711102011009910010010000100000011171701600394890100001004003840038400384003840083
1020440037300000006139407251010010010000100100005005706908040018400374003738115638740101002001000820020016400374003711102011009910010010000100000011171701600394890100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140065400374003738108338745101002001000020020000400374003711102011009910010010000100000000071011611394790100001004003840038400384003840038
1020440037299000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000000071011611394790100001004003840038400384003840075
1020440037300000006139398251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020360400374003711102011009910010010000100000000071011611394790100001004003840038400384003840038
1020440037300000006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100200000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)03181e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002440037300000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730003088843940725100101210012101014850570830404001840037400373813507387671029320100002020000400374003711100211091010100001010640216223947310000104022740085400384003840038
1002440037300000613935325100101010000101000050570690804029840037400373813003387671001020109762022258403664036841100211091010100001003640216263969110000104008440038400384008540038
10024400373000006139407251001010100001010000505706908040018400374003738130033876710010201000020200004003740037111002110910101000010027640316323947310000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000001053940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804001840133401323813003387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmulx v0.2s, v1.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)03191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204400373000000726394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100003071011611394790100001004003840038400384003840038
10204400373001000613940725101001001000010010000500570690814001804003740037381083387451010020010000200200004008840037111020110099100100100001000423071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400183400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
10204400373000000726394072510100100100001001000050057069081400180400374008438108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100000071011711394795100001004003840038400384003840038
1020440037299000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300000061394072510100100100001001000050057069081400180400374003738108338745101002001000020020000400374003711102011009910010010000100003071011611394790100001004003840038400384013440038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)03181e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa7a8a9accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002440037299000014739407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416443947310000104003840038400384003840038
1002440037299000018739407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416433947310000104003840038400384003840038
100244003729900006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000640416433947310000104003840038400384003840038
1002440037300000051539407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416433947310000104003840038400384003840038
1002440037300000110339407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416343947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640316443947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416443947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640416423947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640316343947310000104003840038400384003840038
1002440037300000010539407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000640316433947310000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmulx v0.2s, v8.2s, v9.s[1]
  fmulx v1.2s, v8.2s, v9.s[1]
  fmulx v2.2s, v8.2s, v9.s[1]
  fmulx v3.2s, v8.2s, v9.s[1]
  fmulx v4.2s, v8.2s, v9.s[1]
  fmulx v5.2s, v8.2s, v9.s[1]
  fmulx v6.2s, v8.2s, v9.s[1]
  fmulx v7.2s, v8.2s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)033f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8020420049150952580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511041611200370800001002004120041200412004120041
80204200401504222580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150632580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150422580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150422580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011610200370800001002004120041200412004120041
8020420040150632580100100800001008000050064000002002120040200409983399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150862580100100800001008000050064000002002120040200409973399988010020080000200160000200402004021802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150422580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
8020420040150422580100100800001008000050064000002002120040200409973399988010020080000200160000200402004011802011009910010080000100511011611200370800001002004120041200412004120041
802042004015015125801001008000010080000500640000020021200402004099733999880100200800002001600002004020040118020110099100100800001005110116122003718800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0304080b18191e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242004915600000002372580010108000010800005064000020021200402004099963100208001020800002016000020040200401180021109101080000102304144025020516317200370080000102004120041200412004120041
800242004015500000004125800101080000108000050640000200212004020040999631002080010208000020160000200402004011800211091010800001000000050205165202003702080000102004120041200412004120041
800242004015000000002762580010108000010800005064000020021200402004099963100208001020800002016000020040200401180021109101080000100000005020316313200370080000102004120041200412004120041
80024200401500000000412580010108000010800005064000020021200402004099963100208001020800002016000020040200401180021109101080000100000005020516315200370080000102004120041200412004120041
80024200401500000000412580010108000010800005064000020021200402004099963100208001020800002016000020040200401180021109101080000100000005020316518200370080000102004120041200412004120041
80024200401500000000574258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010000000502041656200370080000102004120041200412004120041
800242004015000000001462580010108000010800005564000020021200402004099963100208001020800002016000020040200401180021109101080000100000005020316320200370080000102004120041200412004120041
8002420040155000000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010020297045059540521201180080000102004120041200412004120041
8002420040155000000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010000000502031637200370080000102004120041200412004120041
80024200401500000000832580010108000010800005064000020021200402004099963100208001020800002016000020040200952180021109101080000100000005020316519200370080000102004120041200412004120041