Firestorm: FMULX (by element, 2S) measurements

Code:

  fmulx v0.2s, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	316	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	82	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	35	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	9	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  fmulx v0.2s, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	6	38740	10100	200	10008	200	20016	40037	40037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	6	38740	10100	200	10008	200	20016	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	6	38741	10100	200	10008	200	20016	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40083
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38115	6	38740	10100	200	10008	200	20016	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40065	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40075
10204	40037	300	0	0	0	0	0	61	39398	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20360	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	30	88	84	39407	25	10010	12	10012	10	10148	50	5708304	0	40018	40037	40037	38135	0	7	38767	10293	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	39473	10000	10	40227	40085	40038	40038	40038
10024	40037	300	0	0	0	61	39353	25	10010	10	10000	10	10000	50	5706908	0	40298	40037	40037	38130	0	3	38767	10010	20	10976	20	22258	40366	40368	4	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	6	39691	10000	10	40084	40038	40038	40085	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	27	640	3	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	105	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40133	40132	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  fmulx v0.2s, v1.2s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40088	40037	1	1	10201	100	99	100	100	10000	100	0	42	3	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	3	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40084	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	17	1	1	39479	5	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40134	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	0	147	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	187	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	515	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	1	103	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	105	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	3	39473	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fmulx v0.2s, v8.2s, v9.s[1]
  fmulx v1.2s, v8.2s, v9.s[1]
  fmulx v2.2s, v8.2s, v9.s[1]
  fmulx v3.2s, v8.2s, v9.s[1]
  fmulx v4.2s, v8.2s, v9.s[1]
  fmulx v5.2s, v8.2s, v9.s[1]
  fmulx v6.2s, v8.2s, v9.s[1]
  fmulx v7.2s, v8.2s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20049	150	95	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	4	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	422	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	63	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	0	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	63	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9983	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	86	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	2	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	151	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	5110	1	16	1	2	20037	18	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20049	156	0	0	0	0	0	0	0	237	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	2	3	0	4	1440	2	5020	5	16	3	17	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	155	0	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	5	16	5	20	20037	0	20	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	276	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	3	16	3	13	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	5	16	3	15	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	3	16	5	18	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	574	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	4	16	5	6	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	146	25	80010	10	80000	10	80000	55	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	3	16	3	20	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	155	0	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	2	0	2	970	4	5059	5	40	5	21	20118	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	155	0	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	3	16	3	7	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	0	83	25	80010	10	80000	10	80000	50	640000	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20095	2	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	3	16	5	19	20037	0	0	80000	10	20041	20041	20041	20041	20041

FMULX (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations