Firestorm: FMULX (by element, 8H) measurements

Code:

  fmulx v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	5	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	2	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	11	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	228	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  fmulx v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	33	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	346	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	3	354	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1	0	21	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	33	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	6	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40083
10024	40037	300	0	0	6	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	1019	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  fmulx v0.8h, v1.8h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	26	9	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40226	300	61	39407	25	10100	100	10006	104	10148	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	5	9	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	124	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	46	6	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	55	9	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	46	3	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10178	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	47	3	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	50	3	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	48	12	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	55	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	48	9	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	156	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	28	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40228
10024	40085	300	0	0	0	61	39398	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38150	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	26	3	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	9	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	0	3	38767	10159	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	0	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fmulx v0.8h, v8.8h, v9.h[1]
  fmulx v1.8h, v8.8h, v9.h[1]
  fmulx v2.8h, v8.8h, v9.h[1]
  fmulx v3.8h, v8.8h, v9.h[1]
  fmulx v4.8h, v8.8h, v9.h[1]
  fmulx v5.8h, v8.8h, v9.h[1]
  fmulx v6.8h, v8.8h, v9.h[1]
  fmulx v7.8h, v8.8h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20318	158	2	0	1	0	6	5	924	528	3	2074	155	80731	123	80505	121	80628	629	644146	1	20310	20361	20354	10028	26	10189	80757	200	80629	202	161258	20354	20360	7	1	80201	100	99	100	100	80000	100	0	0	0	0	2	0	0	0	5114	10	16	10	10	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	155	1	0	1	0	0	0	0	0	2	49	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	0	0	0	5114	10	16	9	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	156	1	0	1	0	0	0	0	0	2	49	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	42	0	9	0	5114	7	16	7	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	0	0	2	1904	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	69	0	5114	9	16	4	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	0	0	2	133	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	4	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	18	0	5114	10	16	10	10	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	3	0	2	49	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	21	0	5114	9	16	9	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	0	0	2	49	45	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	24	0	5114	10	16	9	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	0	0	2	49	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	12	0	5114	9	16	5	9	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	2	0	1	0	0	0	0	0	2	49	25	80100	100	80000	122	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	12	0	5114	9	16	9	4	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	1	0	0	0	0	0	2	70	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	15	2	5114	9	16	9	9	20037	0	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20049	151	0	0	12	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	27	5020	7	16	7	5	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	8	16	6	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	12	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	4	3	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	149	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	21	5020	7	16	6	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	1	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	16	63	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	30	5020	6	16	6	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	24	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	1	0	24	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	516	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	1	3	5020	6	16	6	5	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	30	5020	5	16	5	6	20037	80000	10	20041	20041	20041	20041	20041

FMULX (by element, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations