Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMULX (by element, 8H)

Test 1: uops

Code:

  fmulx v0.8h, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100050073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100000373116113473100040384038403840384038
100440373006134072510001000100053190840184037403732583389510001000200040374037111001100002073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000110073116113473100040384038403840384038
1004403730022834072510001000100053190840184037403732583389510001000200040374037111001100000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmulx v0.8h, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730000033613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007102161139479100001004003840038400384003840038
10204400372990000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
10204400372990000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000003463940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
1020440037300003354613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100037101161139479100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730001021613940725101001001000010010000500570690840018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000033061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001006640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840083
1002440037300006061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001010640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000001019394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037299000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmulx v0.8h, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373006139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001002697101161139479100001004003840038400384003840038
1020440226300613940725101001001000610410148500570690814001804003740037381080338745101002001000020020000400374003711102011009910010010000100597101161139479100001004003840038400384003840038
102044003729912439407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001004667101161139479100001004003840038400384003840038
10204400372996139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001005597101161139479100001004003840038400384003840038
10204400373006139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001004637101161139479100001004003840038400384003840038
10204400373006139407251010010010000100100005005706908140018040037400373810803387451010020010178200200004003740037111020110099100100100001004737101161139479100001004003840038400384003840038
10204400373006139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001005037101161139479100001004003840038400384003840038
102044003730061394072510100100100001001000050057069081400180400374003738108033874510100200100002002000040037400371110201100991001001000010048127101161139479100001004003840038400384003840038
10204400372996139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001005507101161139479100001004003840038400384003840038
10204400372996139407251010010010000100100005005706908140018040037400373810803387451010020010000200200004003740037111020110099100100100001004897101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300000156394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038
1002440037300000613940725100101010000101000050570690814001840037400373813003387671001020100002020000400374003711100211091010100001028006403163339473010000104003840038400384003840228
100244008530000061393982510010101000010100005057069081400184003740037381500338767100102010000202000040037400371110021109101010000102006403163339473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690814001840037400373813003387671001020100002020000400374003711100211091010100001026306403163339473010000104003840038400384003840038
100244003729900961394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400184003740037381300338767101592010000202000040037400371110021109101010000102006403163339473010000104003840038400384003840038
100244003730000061394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038
100244003729900061394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038
100244003729900061394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038
1002440037300000726394072510010101000010100005057069081400184003740037381300338767100102010000202000040037400371110021109101010000101006403163339473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmulx v0.8h, v8.8h, v9.h[1]
  fmulx v1.8h, v8.8h, v9.h[1]
  fmulx v2.8h, v8.8h, v9.h[1]
  fmulx v3.8h, v8.8h, v9.h[1]
  fmulx v4.8h, v8.8h, v9.h[1]
  fmulx v5.8h, v8.8h, v9.h[1]
  fmulx v6.8h, v8.8h, v9.h[1]
  fmulx v7.8h, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420318158201065924528320741558073112380505121806286296441461203102036120354100282610189807572008062920216125820354203607180201100991001008000010000002000511410161010200370800001002004120041200412004120041
8020420040155101000002492580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000010005114101699200370800001002004120041200412004120041
8020420040156101000002492580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000042090511471679200370800001002004120041200412004120041
802042004015010100000219042580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000690511491649200370800001002004120041200412004120041
80204200401501010000021332580100100800001008000050064000012002120040200409973399988010020080000200160000200402004041802011009910010080000100000000180511410161010200370800001002004120041200412004120041
8020420040150101000302492580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000210511491699200370800001002004120041200412004120041
80204200401501010000024945801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000002405114101699200370800001002004120041200412004120041
8020420040150101000002492580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000120511491659200370800001002004120041200412004120041
8020420040150201000002492580100100800001228000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000120511491694200370800001002004120041200412004120041
8020420040150101000002702580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000152511491699200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200491510012412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010000275020716752003780000102004120041200412004120041
800242004015000041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000005020816662003780000102004120041200412004120041
8002420040150001241258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000435020516562003780000102004120041200412004120041
8002420040149000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010000215020716662003780000102004120041200412004120041
80024200401501004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100016635020516562003780000102004120041200412004120041
8002420040150000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010000305020616662003780000102004120041200412004120041
8002420040150000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010000245020516562003780000102004120041200412004120041
8002420040150000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010010245020516562003780000102004120041200412004120041
8002420040150000516258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000135020616652003780000102004120041200412004120041
8002420040150000412580010108000010800005064000012002120040200409996310020800102080000201600002004020040118002110910108000010000305020516562003780000102004120041200412004120041