Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMULX (scalar, D)

Test 1: uops

Code:

  fmulx d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e5051schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100440373000613407402125100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
100440373100613407025100010001000531908040184037403732583389510001000200040374037111001100000073116223473100040384038403840384038
1004403730006134070251000100010005319080401840374037325833895100010002000403740371110011000012073216223473100040384038403840384038
100440373000613407025100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
100440373000613407025100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
100440373000613407025100010001000531908040184037403732583389510001000200040374037111001100000073217223473100040384038403840384038
1004403731018613407025100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
100440373003613407025100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
1004403730001453407025100010001000531908040184037403732583389510001000200040374037111001100000073216223473100040384038403840384038
100440373000613407025100010001000531908140184037403732583389510001000200040374037111001100000073216223473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmulx d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300001533940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000607101161139479100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100001507101161139479100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000307101161139479100001004003840038400384003840038
102044003730000613940725101001001000010010000681570830404001840037400373810833874510100200100002002000040037400371110201100991001001000010000307101161139479100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000607101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000010507101161039479100001004003840038400384003840038
1020440037300006139389251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100008707101161139479100001004003840038400384003840038
1020440037300006313940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000307101161139479100001004003840038400384003840038
102044003729900613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010020007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000018607101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000640316223947310000104003840038400384003840038
1002440037299061394072510010101000010100005057069084001840037400373813033876710010201000020200004003740037111002110910101000010000150640216223947310000104003840038400384003840038
100244003730006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000093640216223947310000104003840038400384003840038
1002440037300061394072510010101000010100005057069084001840037400373813033876710010201000020200004003740037111002110910101000010000186640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050571109640018400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000015640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100003640216223954110000104003840038400384003840083
100244003730006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001003300640216223947310000104003840038400384003840038
100244003730006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001003100640216223947310000104003840038400384003840038
1002440037299061394072510010101000010100005057069084001840037400373813033876710010201000020200004003740037111002110910101000010000129640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmulx d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300061394072510100100100001001044450057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000100071011601394790100001004003840038400384003840038
1020440037299961394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381083387451010020010000204200004003740037111020110099100100100001000400071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010005200071011611398140100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010004200071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000290071011611394790100001004003840038400384003840038
10204400372990613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010003600071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010002100071011611394790100001004003840038400384003840038
10204400372990613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010003300071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730001663940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037211002110910101000010000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010030640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000823940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400372990613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
100244003730007683940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038
10024400373000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000640216223947310000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmulx d0, d8, d9
  fmulx d1, d8, d9
  fmulx d2, d8, d9
  fmulx d3, d8, d9
  fmulx d4, d8, d9
  fmulx d5, d8, d9
  fmulx d6, d8, d9
  fmulx d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500042258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051103163220037800001002004120041200412004120041
802042004015000109258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102162320037800001002004120041200412004120041
802042004015000105258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102162220037800001002004120041200412004120041
80204200401500042258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102163220037800001002004120041200412004120041
80204200401500084258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102163220037800001002004120041200412004120041
802042004015000232258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102162220037800001002004120041200412004120041
802042004015000422580100100800001008000050064000002002120040200409973310026801002008000020016000020040200401180202100991001008000010000051102163320037800001002004120041200412004120041
80204200401500063258010010080000100800005006400000200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102162220037800001002004120041200412004120041
802042004015000390258010010080000100800005006400001200212004020040997339998801002008000020016000020040200401180201100991001008000010000051102162220037800001002004120041200412004120041
802042004015000107258010010080000100801055006400001200212004020040997339998801002008000020016000020040200401180201100991001008000010000451102163220037800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420049150000622580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001000005020021611200370080000102004120041200412004120041
80024200401500005442580010108000010800005064000000200212004020040999631002080010208000020160000200402004011800211091010800001000005055021611200370080000102004120041200412004120041
80024200401500005702580010108000010800005064000000200212004020040999631002080010208000020160000200402004011800211091010800001022305020011611200370080000102004120041200412004120041
80024200401500001062580010108000010800005064000000200212004020040999631002080010208000020160000200402004011800211091010800001000005020011611200370080000102004120041200412004120041
80024200401500005142580010108000010800005064000000200212004020040999631002080010208000020160000200402009311800211091010800001000005020011622200370080000102004120041200412004120041
80024200401501006225800101080000108000050640000002002120040200409996310020800102080000201600002004020040118002110910108000010003050200116112003720080000102004120041200412004120041
80024200401500005512580010108000010800005064000011200212004020040999631002080010208000020160000200402004011800211091010800001000005020011611200370080000102004120041200412004120041
80024200401500001062580010108000010801205064000000200212004020040999631002080010208000020160000200402004011800211091010800001000005020021622200370080000102004120041200412004120041
8002420040150000412580010108000010800005064000000200212004020040999631002080010208000020160000200402004011800211091010800001000005020011622200370080000102009320041200412004120041
80024200401500001712580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001000005020011611200370080000102004120041200412004120041