Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMULX (scalar, H)

Test 1: uops

Code:

  fmulx h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10044037303361340725100010001000531908401840374037325833895100010002000403740371110011000073216113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403731061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403731061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730961340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730082340725100010001000531908401840374037325833895100010002000403740371110011000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmulx h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400842990613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001007071011611394790100001004003840038400384003840038
102044003730007263940725101001001000010010000500570690814001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400372990613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
102044003729901843940725101001001000010010000500570690804001804003740037381083387451010020010000200213164003740037111020110099100100100001002071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690814001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690814001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001804003740037381083387451010020010000200200004003740037111020110099100100100001000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300008239407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640316223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020106482020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037299036139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020104832020000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400372990486139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400854003840038
1002440037300006139407251001010100001010000505706908400184003740037381303387671001020100002020000400374003711100211091010100001000000640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmulx h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
10204400372990053639407251010010010000100100005005706908040018400374003738108338745101002001000021420000400374003711102011009910010010000100000073411611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394791100001004003840038400384003840038
1020440037300008239407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037299006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100010071011611394790100001004003840038400384003840038
1020440037300006139389251010010010000100100005005706908040018400374003738108338745101002001000020020000402274003711102011009910010010000100000071011611394790100001004003840038400384003840038
1020440037300006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400372990613940745100101010000151014850570690804005304008340037381300338767100102010000202000040037400371110021109101010000100296402162239473010000104003840038400384003840038
10024400372990613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037300121033940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400372990613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239545010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmulx h0, h8, h9
  fmulx h1, h8, h9
  fmulx h2, h8, h9
  fmulx h3, h8, h9
  fmulx h4, h8, h9
  fmulx h5, h8, h9
  fmulx h6, h8, h9
  fmulx h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000000000422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511031611200370800001002004120041200412004120041
80204200401500000031080422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
8020420040150000000001472580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
80204200401500000011400422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
802042004015000000000422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
802042004015000000000422580100100800001008000050064000012018702004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
802042004015000000000422580100100800001008000050064000012002132004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
802042004015000000000422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
80204200401500000000026652580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041
802042004015000000000422580100100800001008000050064000012002102004020040997339998801002008000020016000020040200401180201100991001008000010000000000511011611200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004915000004125800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010200005020816792003780000102009120041200412004120041
800242004015000304125800101080000108000050640000012002120040200401003631002080010208000020160000200402004011800211091010800001000000502012161182003780000102004120041200412006620041
8002420040150000884125800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010010005020141612142003780000102004120041200412004120093
800242004015000004125800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010000005020131613122003780000102004120041200412004120041
8002420040150000018245800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010000005020111611112003780000102004120041200412004120041
800242004015000004125800101080000108000050640000112002120040200409996310020800102080000201600002004020040118002110910108000010000005020131612122003780000102004120041200412004120041
80024200401500000412580010108000010800005064000011201042004020040999631002080010208000020160000200402004011800211091010800001000000502010166122003780000102004120041200412004120041
80024200401500000412580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001000000502091610122003780000102004120041200412004120041
800242004015100004125800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010000305020131611132003780000102004120041200412004120041
800242004015000004125800101080000108000050640000012002120040200409996310020800102080000201600002004020040118002110910108000010000005020111612122003780000102004120041200412004120041