Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
fmulx v0.2d, v0.2d, v1.2d
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 1004 | 4037 | 30 | 0 | 103 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 156 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 31 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 31 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 156 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 147 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 31 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
| 1004 | 4037 | 30 | 0 | 61 | 3407 | 25 | 1000 | 1000 | 1000 | 531908 | 1 | 4018 | 4037 | 4037 | 3258 | 3 | 3895 | 1000 | 1000 | 2000 | 4037 | 4037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 3473 | 1000 | 4038 | 4038 | 4038 | 4038 | 4038 |
Code:
fmulx v0.2d, v0.2d, v1.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 4.0037
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 12 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 299 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38143 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 1 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 299 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 0 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 299 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 84 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 0 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40081 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
Result (median cycles for code): 4.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | 1e | 1f | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 89 | 39398 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 11 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40084 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 5 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 733 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 299 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 299 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 8 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 10 | 16 | 10 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 299 | 1 | 1 | 0 | 0 | 2 | 68 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 644 | 8 | 16 | 8 | 10 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
Code:
fmulx v0.2d, v1.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 4.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 147 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40085 | 300 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 3 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 726 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40229 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 202 | 10000 | 204 | 20000 | 40037 | 40037 | 3 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10204 | 40037 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 39407 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 5706908 | 40018 | 0 | 40037 | 40037 | 38108 | 3 | 38745 | 10100 | 200 | 10000 | 200 | 20000 | 40037 | 40037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 1 | 0 | 710 | 1 | 16 | 1 | 1 | 39479 | 0 | 10000 | 100 | 40038 | 40038 | 40038 | 40038 | 40038 |
Result (median cycles for code): 4.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 1348 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 5 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 5 | 3 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10025 | 40037 | 300 | 0 | 0 | 0 | 61 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 0 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 0 | 0 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 61 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 0 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10158 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 0 | 0 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 555 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 0 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 0 | 0 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 1425 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 0 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 0 | 0 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 299 | 0 | 0 | 0 | 1379 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 5 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 0 | 0 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 894 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 0 | 0 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 5 | 3 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 61 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 5 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 5 | 3 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 1866 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 5 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 5 | 3 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
| 10024 | 40037 | 300 | 0 | 0 | 0 | 61 | 39407 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 5706908 | 1 | 5 | 40018 | 40037 | 40037 | 38130 | 3 | 38767 | 10010 | 20 | 10000 | 20 | 20000 | 40037 | 40037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 5 | 3 | 2 | 16 | 2 | 2 | 39473 | 10000 | 10 | 40038 | 40038 | 40038 | 40038 | 40038 |
Count: 8
Code:
fmulx v0.2d, v8.2d, v9.2d fmulx v1.2d, v8.2d, v9.2d fmulx v2.2d, v8.2d, v9.2d fmulx v3.2d, v8.2d, v9.2d fmulx v4.2d, v8.2d, v9.2d fmulx v5.2d, v8.2d, v9.2d fmulx v6.2d, v8.2d, v9.2d fmulx v7.2d, v8.2d, v9.2d
movi v8.16b, 9 movi v9.16b, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | 3a | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 20058 | 150 | 2 | 133 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 10 | 16 | 6 | 9 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 5 | 16 | 5 | 9 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 70 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 7 | 16 | 9 | 5 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 70 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 11 | 16 | 4 | 9 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 7 | 16 | 7 | 4 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 9 | 16 | 10 | 5 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 11 | 16 | 11 | 4 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 10026 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 10 | 16 | 11 | 4 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 10 | 16 | 10 | 4 | 20037 | 0 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80204 | 20040 | 150 | 2 | 47 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 20021 | 0 | 20040 | 20040 | 9973 | 3 | 9998 | 80100 | 200 | 80000 | 200 | 160000 | 20040 | 20040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 5114 | 10 | 16 | 10 | 9 | 20037 | 22 | 80000 | 100 | 20041 | 20041 | 20041 | 20041 | 20041 |
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | ac | cf | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 20049 | 150 | 0 | 0 | 62 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 15 | 16 | 0 | 0 | 0 | 16 | 14 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 469 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 2 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 16 | 16 | 0 | 0 | 0 | 6 | 4 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 41 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 16 | 16 | 0 | 0 | 0 | 6 | 14 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 41 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 16 | 16 | 0 | 0 | 0 | 16 | 4 | 20037 | 0 | 20 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 41 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 1 | 0 | 5020 | 0 | 0 | 6 | 16 | 0 | 0 | 0 | 6 | 3 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 150 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 16 | 16 | 0 | 0 | 0 | 16 | 3 | 20037 | 0 | 20 | 8 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 41 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 6 | 16 | 0 | 0 | 0 | 6 | 13 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 62 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 6 | 16 | 0 | 0 | 0 | 16 | 3 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 104 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 14 | 16 | 0 | 0 | 0 | 13 | 3 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |
| 80024 | 20040 | 150 | 0 | 0 | 41 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20021 | 20040 | 20040 | 9996 | 0 | 3 | 10020 | 80010 | 20 | 80000 | 20 | 160000 | 20040 | 20040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 0 | 0 | 5020 | 0 | 0 | 16 | 16 | 0 | 0 | 0 | 16 | 3 | 20037 | 0 | 0 | 0 | 80000 | 10 | 20041 | 20041 | 20041 | 20041 | 20041 |