Firestorm: FMULX (vector, 2S) measurements

Code:

  fmulx v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	147	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	124	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	0	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  fmulx v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	1364	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	319	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	361	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1284	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	82	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1302	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	9	407	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	3	1334	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1353	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	1310	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10172	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	22	20322	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	3	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	4	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	40088	40085	40037	38130	3	38767	10010	20	10323	22	20324	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	2	3790	0	0	663	5	32	4	4	39473	1	10000	10	40463	40463	40497	40464	40356
10024	40462	303	0	0	1	8	9	1200	880	6519	39326	199	10042	15	10054	14	11184	71	5719472	40298	40451	40271	38169	40	38931	11049	24	11395	24	22266	40512	40458	10	1	10021	10	9	10	10	10000	10	0	1	2	32060	0	0	820	8	89	4	5	39833	3	10000	10	40467	40322	40466	40465	40467
10024	40463	303	1	1	1	9	9	1059	792	7295	39326	216	10065	12	10060	18	11332	72	5717780	40333	40461	40084	38165	45	38941	11348	24	11594	30	22928	40463	40465	10	1	10021	10	9	10	10	10000	10	2	1	0	17788	0	0	640	3	16	2	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	4	4	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  fmulx v0.2s, v1.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40077	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	202	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	712	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40084	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	12	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	5	16	10	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	5	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	12	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	727	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	12	16	10	12	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	104	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	644	10	16	10	5	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	2	62	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	8	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	644	10	16	10	10	39473	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fmulx v0.2s, v8.2s, v9.2s
  fmulx v1.2s, v8.2s, v9.2s
  fmulx v2.2s, v8.2s, v9.2s
  fmulx v3.2s, v8.2s, v9.2s
  fmulx v4.2s, v8.2s, v9.2s
  fmulx v5.2s, v8.2s, v9.2s
  fmulx v6.2s, v8.2s, v9.2s
  fmulx v7.2s, v8.2s, v9.2s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20060	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	2	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	9	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	141	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20072	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	707	25	80100	100	80000	100	80000	500	640000	1	20021	0	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20049	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	19	16	0	0	19	18	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	19	16	0	0	19	19	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	14	16	0	0	19	20	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	21	16	0	0	17	19	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	19	16	0	0	15	20	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	21	16	0	0	19	20	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	533	5020	0	0	0	19	16	0	0	22	19	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	6	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	3	0	0	20	16	0	0	20	21	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	19	16	0	0	15	20	20037	0	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	0	0	18	16	0	0	18	14	20037	0	0	80000	10	20041	20041	20041	20041	20041

FMULX (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations