Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FMUL (by element, 2S)

Test 1: uops

Code:

  fmul v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a9c2cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100440373036134072510001000100053190814018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
100440373106134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110002073216223473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730025134072510001000100053190804018403740373258338951000100020004037403711100110000273216223473100040384038403840384038
100440373096134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730025134072510001000100053190804018403740373258338951148100020004037403711100110000073216223473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmul v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)030b181e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000107101161139479100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000107101161139479100001004003840038400384003840038
10204400373000006139407251010010010000100101485005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100004607101161139479100001004003840038400384003840038
1020440037300000823940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400841110201100991001001000010000107101161139479100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000107101161139479100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000207101161139479100001004003840038400384003840038
1020440037300000613940725101181001000010010148500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000107101161139479100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000307101161139479100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000107101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)0318191e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000025139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100010640216223947310000104003840038400384003840038
1002440037299000613940725100101210000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010003512640216223947310000104003840038400384003840038
10024400373000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100013640216223947310000104003840038400384003840038
10024400372990006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100030640216223947310000104003840038400384003840038
10024400373000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100030640216223947310000104003840038400384003840038
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100030640216213947310000104003840038400384003840038
100244003730000010539407251001010100181010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000640216223947310000104003840038400384003840038
10024400373000006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100010640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmul v0.2s, v1.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1020440037300082394072510100100100001001000051157069081400184003740037381087338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394791100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001014750057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)03090b1e3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8acc2cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024400373000000613940710110010101000610100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001004000000640216223947310000104003840038400384003840038
10024400373000000726394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000300640216223947310000104003840038400384003840038
10024400372990000209394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037300000061393712510010121000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000003000640216213947310000104003840038400384003840038
10024400372990000726394072510010101000010100005057069084001804003740037381303387671001020101752020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037300000061394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000000000640216223947310000104003840038400384003840038
1002440037299000061394072510010101000010100005057069084001804003740037381303387671001020100002020000400374003711100211091010100001000003000640216223947310000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmul v0.2s, v8.2s, v9.s[1]
  fmul v1.2s, v8.2s, v9.s[1]
  fmul v2.2s, v8.2s, v9.s[1]
  fmul v3.2s, v8.2s, v9.s[1]
  fmul v4.2s, v8.2s, v9.s[1]
  fmul v5.2s, v8.2s, v9.s[1]
  fmul v6.2s, v8.2s, v9.s[1]
  fmul v7.2s, v8.2s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802042006015000000098625801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511031611200370800001002004120041200412004120041
80204200401500000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511021611200370800001002004120041200412004120041
802042004015000000080125801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000017225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
80204200401500000006325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
8020420040150000000108325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000049025801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
80204200401500000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
8020420040149000000104425801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000012825801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0304193f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accfd5d6dbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242004915010127258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502041633320037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031613320037080000102004120041200412004120041
800242004015000125258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031623220037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031603220037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031603320037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001010502031612320037080000102004120041200412004120041
800242004015000106258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502021614320037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031613220037080000102004120041200412004120041
80024200401500041258001010800841080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502031613320037080000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020160000200402004011800211091010800001000502021613320037080000102004120041200412004120041