Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FMUL (by element, 8H)

Test 1: uops

Code:

  fmul v0.8h, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03181e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073316113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319081401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373003613407251000100010005319081401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
100440373003613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmul v0.8h, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)031e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400372990061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730021061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400372990061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)030b1e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002440037300012103394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
100244003730006613940725100101010000101000050570690814001840178400373813020387861001020100002020000400374003711100211091010100001036006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400372990061394072510010101000010100005057069080400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002020000400374003711100211091010100001010006402162239473010000104003840038400384003840038
10024400372990061394072510010101000010100005057082910400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400184003740037381303387671001020100002020000400374003711100211091010100001000006402162239473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmul v0.8h, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acbranch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007102161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001001007101161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001001007101161139479100001004003840038400384003840038
1020440037300158239407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003730006139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003729906139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001000007101161139479100001004003840038400384003840038
102044003729906139407251010010010000100100005005706908400184003740037381083387451010020010000200200004003740037111020110099100100100001005007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire (01)cycle (02)03181e3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8accdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024400373000006313940725100101010000101000050570690814001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162139473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690814001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037300000613940725100101010000101000050570690804002204003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299000613940725100101010000101000050570690804001804003740037381300338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037300000613940725100101010000101000050570690814001804003740037381300338767100102010000202000040037400371110021109101010000100016402162239473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmul v0.8h, v8.8h, v9.h[1]
  fmul v1.8h, v8.8h, v9.h[1]
  fmul v2.8h, v8.8h, v9.h[1]
  fmul v3.8h, v8.8h, v9.h[1]
  fmul v4.8h, v8.8h, v9.h[1]
  fmul v5.8h, v8.8h, v9.h[1]
  fmul v6.8h, v8.8h, v9.h[1]
  fmul v7.8h, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03080b181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200601500000042258010010080000100800005006400002002102004020040997339998801002008000020016000020040200401180201100991001008000010000300660051102161120037800001002004120041200412004120041
8020420040150000004225801001008000010080000500640000200210200402004099733999880100200800002001600002004020040118020110099100100800001000022000051101161120037800001002004120041200412004120041
8020420040150000004225801001008000010080000500640000200210200402004099733999880100200800002001600002004020040118020110099100100800001000026030051101161120037800001002004120041200412004120041
8020420040150000004225801001008000010080000500640000200210200402004099733999880100200800002001600002004020040118020110099100100800001000031000051101161120037800001002004120041200412004120041
802042004015000000422580100100800001008000050064000020021020040200409973399988010020080000200160000200402004011802011009910010080000100000030151101161120037800001002004120041200412004120041
8020420040150000001032580100100800001008000050064000020021020040200409973399988010020080000200160000200402004011802011009910010080000100003201110051101161120037800001002004120041200412004120041
80204200401500000042258010010080000100800005006400002002102004020040997311999880100200800002001600002004020040118020110099100100800001000026000051101162120037800001002004120041200412004120041
802042004015000000422580100100800001008000050064000020021020040200409973399988010020080000200160000200402004011802011009910010080000100000000051101161120037800001002004120041200412004120041
8020420040150000001702580100100800001008000050064000020021020040200409973399988010020080000200160000200402004011802011009910010080000100000000051101161120037800001002004120041201432004120041
802042004015000000422580100100800001008000050064000020021020040200409973399988010020080000200160000200402004011802011009910010080000100000000051101161120037800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)030b1e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8accfd0d2d5d6d9ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8002420049150000412580012108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100271355020501616012122003780000102004120041200412004120041
80024200401500004125800101080000108000050640000015200212004020040999631002080010208000020160000200402014621800211091010800001002465020501216012152003780000102004120041200412004120041
8002420040150000412580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100005020501816012122003780000102004120041200412004120041
8002420040150000412580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100005020511316015112003780000102004120041200412004120041
8002420040150000412580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100005020511716014162003780000102004120041200412004120041
800242004015000041258001010800001080000506400000152002120040200409996310020800102080000201600002004020040118002110910108000010027905020511616016132003780000102004120041200412004120041
8002420040150000832580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100005020511216014152003780000102004120041200412004120041
8002420040150000412580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000100005020511316014162003780000102004120041200412004120041
8002420040150000412580010108000010800005064000001520021200402004099963100208001020800002016000020040200401180021109101080000102005020511316016132003780000102004120041200412004120041
80024200401500004125800101080000108000050640000115200212004020040999631002080010208000020160000200402004011800211091010800001000815020511616016132003780000102004120041200412004120041