Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMUL (scalar, H)

Test 1: uops

Code:

  fmul h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000001073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
10044037308761340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403731061340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403730361340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000000096116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110021000000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403730061340725100010001000531908401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmul h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730000006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003729900006139407251010010010000100100005005706908140018400374003738108338745101002001000020021296400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010006100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100107101161139494100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004008540038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384008540038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020662400374003711102011009910010010000100007102161139479100001004003840038400384003840038
102044003731100006139407251010010010000100100005005706908040018400374003738108338745102512001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
1020440037299000097939407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373100000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400372990000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162139473010000104003840038400384003840038
10024400373000000000613940725100101010000101000050570690840018400374003738130338767100102010643202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000000006139407251001010100001010000505706908400184003740037381302638767100102010000202034440037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000000002513940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400372990000000613940725100101010000101000050570690840018400374003738130338767100102010491202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000000001243940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400373000000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmul h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)a9acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400372991061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100020071002162239479100001004003840038400384003840038
10204400373000089394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
102044003730000880394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002041049020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
102044003730000726394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002001016620020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381080338745101002001000020020000400374003711102011009910010010000100000071002162239479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000026239407251001010100001010000505706908140018400374003738130033876710010201000020200004003740037111002110910101000010000000064411169939473010000104003840038400384003840038
10024400373000002623940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000000006441116111139473010000104003840038400384003840038
1002440037300000262394072510010101000010100005057069080400184003740037381300338767100102010000202000040037400371110021109101010000100000030644616111139473010000104003840038400384003840038
1002440037300000262394072510010101000010100005057069080400184003740037381300338767100102010000202000040037400371110021109101010000100000000644616111139473010000104003840038400384003840038
10024400372990002347394072510010101000010100005057069080400184003740037381300338767100102010160202000040037400371110021109101010000100000000644111691139473010000104003840038400384003840038
1002440037300000262394072510010101000010100005057069080400184003740037381300338767100102010000202000040037400371110021109101010000100000000644616111139473010000104003840038400384003840038
10024400372990002623940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000000006441116111139473010000104003840038400384003840038
10024400373000002623940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000000006441116111139617010000104003840038400384003840038
1002440037300000262394072510010101000010100005057069080400184003740037381300338767100102010000202000040037400371110021109101010000100000000644616111139473010000104003840038400384003840038
10024400373000002623940725100101010000101000050570690804001840037400373813003387671001020100002020000400374003711100211091010100001000000006441116111139473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmul h0, h8, h9
  fmul h1, h8, h9
  fmul h2, h8, h9
  fmul h3, h8, h9
  fmul h4, h8, h9
  fmul h5, h8, h9
  fmul h6, h8, h9
  fmul h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049150000015004225801001008000010080000500640000020144200402004099733999880100200800002001600002004020040118020110099100100800001002000053005110228112008917800001002010120133201142004120041
80204200401500000300026243801001008000010080106500640000120021200402004099858999880100200800002001600002004020040118020110099100100800001000000000512711611200370800001002004120041200412004120041
802042004015000000004225801001008000010080000500640000020021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
8020420040150000015004225801001008000010080000500640000020021200402004099733999880100200800002001600002004020040118020110099100100800001000000060511011611200370800001002004120041200412004120041
802042004015000000008425801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000004225801001008000012180000500640000120021200402009399733999880210200800002001600002004020040118020110099100100800001000000000511021611200370800001002004120041200412025020041
802042004015000000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511011611200370800001002004120041200412004120041
802042004015000000004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000010000511012511200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000816762003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000816782003780000102004120041200412004120041
8002420040150104125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000516572003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000616882003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000316662003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000616572003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000516772003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000716882003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000516562003780000102004120041200412004120041
8002420040150004125800101080000108000050640000102002120040200409996310020800102080000201600002004020040118002110910108000010502000516872003780000102004120041200412004120041