Firestorm: FMUL (vector, 2D) measurements

Code:

  fmul v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	2	2	2	0	2	3520	2	79	2	40	2	1	3499	1000	4086	4085	4085	4122	4086
1004	4085	30	1	0	0	1	1	171	88	0	902	3398	45	1006	1006	1148	533304	1	4053	4084	4084	3262	8	3915	1011	1163	2328	4085	4085	1	1	1001	1000	0	4	0	1	0	3583	4	94	1	24	1	1	3531	1000	4086	4086	4085	4085	4084
1004	4085	31	0	0	0	1	1	138	0	0	873	3398	49	1006	1006	1148	531908	0	4053	4084	4085	3269	7	3914	1000	1160	2436	4084	4085	2	1	1001	1000	0	2	0	0	0	3498	4	73	1	24	2	1	3526	1000	4074	4085	4086	4086	4074
1004	4085	31	1	0	0	1	1	153	88	0	881	3407	44	1006	1006	1148	533304	1	4053	4084	4084	3262	8	3906	1096	1160	2000	4085	4084	2	1	1001	1000	0	0	2	1	0	3535	2	79	1	24	1	2	3507	1000	4038	4038	4085	4084	4084
1004	4085	31	1	0	0	1	1	168	88	1	884	3407	45	1006	1006	1148	533304	1	4053	4085	4084	3262	7	3915	1148	1161	2322	4084	4084	2	1	1001	1000	2	4	2	0	0	3590	2	94	1	24	1	1	3567	1000	4038	4086	4084	4085	4085
1004	4073	31	1	1	1	1	1	177	88	1	948	3398	25	1006	1006	1148	533304	1	4053	4037	4037	3273	6	3915	1148	1163	2320	4085	4083	2	1	1001	1000	0	2	0	1	2	3720	2	94	4	24	1	1	3499	1000	4085	4086	4086	4085	4074
1004	4120	30	1	0	1	0	0	141	88	0	1525	3398	25	1000	1006	1148	533304	1	4053	4037	4084	3273	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	0	0	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  fmul v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	105	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	191	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	107	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	25	38722	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39534	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	368	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	1	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	126	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	6	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40086	299	0	0	0	104	1072	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40133	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	126	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	935	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	172	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	204	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	84	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	1	16	1	1	39748	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	197	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	1	2	39511	10000	10	40038	40038	40038	40038	40038
10024	40037	300	15	126	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	170	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	548	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	42	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10172	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  fmul v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	280	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	84	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	170	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	2	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	0	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	21	350	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	84	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	1	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40084	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	726	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: throughput

Count: 8

Code:

  fmul v0.2d, v8.2d, v9.2d
  fmul v1.2d, v8.2d, v9.2d
  fmul v2.2d, v8.2d, v9.2d
  fmul v3.2d, v8.2d, v9.2d
  fmul v4.2d, v8.2d, v9.2d
  fmul v5.2d, v8.2d, v9.2d
  fmul v6.2d, v8.2d, v9.2d
  fmul v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	2	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	63	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	27	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	2	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	0	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	42	25	80100	100	80000	100	80000	500	640000	1	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	15	0	9	5110	1	16	1	1	20037	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20049	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	7	3	16	3	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	3	16	3	2	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	3	16	3	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	3	16	3	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	4693	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	2	16	3	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	62	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	3	16	2	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	3	0	62	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	2	16	3	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	0	3	16	2	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	3	5020	0	3	16	2	3	20037	0	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	0	0	0	0	0	83	25	80010	10	80000	10	80105	50	640000	0	20021	20040	20103	9996	3	10048	80117	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	4	0	5020	0	3	16	2	3	20037	2	80000	10	20041	20041	20041	20041	20103

FMUL (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations