Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMUL (vector, 4S)

Test 1: uops

Code:

  fmul v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)0918191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403731000018613407251000100010005319081401840374037325833895100010002000403740371110011000000073216113473100040384038403840384038
100440373000000613407251000100010005319080401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
100440373000000613407251000100010005319081401840374037325833895100010002000403740372110011000000373116113473100040384038403840384038
100440373000000613407251000100010005319081401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
100440373100000613407251000100010005319081401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
100440373000000613407251000100010005319080401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
100440373000000613407251000100010005319081401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
100440373000000613407251000100010005319081401840374037325833914100010002000403740371110011000000073116113473100040384038403840384038
100440373000000613407251000100010005319081401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038
1004403730000054613407251000100010005319081401840374037325833895100010002000403740371110011000000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmul v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010003071011611394790100001004003840038400384003840038
10204400373000007263940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400373110201100991001001000010000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037299000012065653933519810068171001816113327657180761403334041540454381433838936113472011455222258840320403671111002110910101000010203143244828504575539800310000104046540466404994050940467
10024404643030110911977047962393711841006917100541310888935719472140158405114045338171443893311215241146820229084046440463811002110910101000010220203086008314885539799410000104060540510405464022640038
100244003729900000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404163439473010000104003840038400854003840038
100244003730010000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404163439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038
100244003730000000061394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000006404164439473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmul v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003729902005363940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
10204400843000000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100004120071011612394790100001004003840038400384003840038
10204400373000000613940763101431001000010010000500570690804005340037400373811233874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
102044003730000006139407631013310010000100100005005706908040018400374003738108123874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
10204400373000000103394072510100100100001001000050057069080400184003740037381133387451010020010000200200004003740037111020110099100100100001000001350071011611394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300006139407251001010100001010000505706908140018040037400373813033876710010201000020200004003740037111002110910101000010007500640316333947310000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001804003740037381303387671001020100002020000400374003711100211091010100001000000640316333947310000104003840038400384003840038
10024400373006021439407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010003000640316333947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010001500640316333947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010002700640316333947310000104003840038400384003840038
1002440037300008239407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010003300640316313947310000104003840038400384003840038
1002440037300006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010002700640316333947310000104003840038400384003840038
1002440037299006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740081111002110910101000010002700640316333947310000104003840038400384003840038
10024400372990886139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010002700640316333947310000104003840038400384003840038
10024400373000072639407251001010100001010000505706908140018040037400373813033876710010201000020200004003740037111002110910101000010102100640316333947310000104003840038400854003840038

Test 4: throughput

Count: 8

Code:

  fmul v0.4s, v8.4s, v9.4s
  fmul v1.4s, v8.4s, v9.4s
  fmul v2.4s, v8.4s, v9.4s
  fmul v3.4s, v8.4s, v9.4s
  fmul v4.4s, v8.4s, v9.4s
  fmul v5.4s, v8.4s, v9.4s
  fmul v6.4s, v8.4s, v9.4s
  fmul v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200801500000000002432580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000051141216109200370800001002004120041200412004120041
802042004015000000003602432580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000051149161010200370800001002004120041200412004120041
802042004015000000000024325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511471674200370800001002004120041200412004120041
8020420040150000000051024325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000002000511410161111200370800001002004120041200412004120041
8020420040150000000000216925801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511411161111200370800001002004120041200412004120041
8020420040150000000000212725801001008000010280000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511471677200370800001002004120041200412004120041
802042004015000000000024325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511411161011200370800001002004120041200412004120041
8020420040150000000027024325801001008008810080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000000000511410161010200370800001002004120041200412004120041
802042004015000000000021272580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000200051141116117200370800001002004120041200412004120041
80204200401500000000002432580100100800001008000050064000012002120040200409973399988010020080000200160000200402004011802011009910010080000100000000051147161010200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420049150000062258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020416672003780000102004120041200412004120041
8002420040150000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020616882003780000102004120041200412004120041
8002420040150000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020816782003780000102004120041200412004120041
8002420040150000083258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020616782003780000102004120041200412004120041
80024200401500000104258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020516852003780000102004120041200412004120041
8002420040150009083448001010800001080000506400002002120040200409996310020800102080107201600002004020040118002110910108000010005020616662003780000102004120041200412004120041
80024200401500000104258001010800841080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020616772003780000102004120041200412004120041
8002420040156000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020816762003780000102004120041200412004120041
8002420040150000041258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020716672003780000102004120041200412004120041
80024200401500000125258001010800001080000506400002002120040200409996310020800102080000201600002004020040118002110910108000010005020516652003780000102004120041200412004120041