Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMUL (vector, 8H)

Test 1: uops

Code:

  fmul v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403730006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
10044037300010734072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100020004037403711100110000079216223473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
10044037300017034072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403731006134072510001000100053190814018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100020004037403711100110000073216223473100040384038403840384038

Test 2: Latency 1->2

Code:

  fmul v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300000611394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000124394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
102044003730000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000214394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000250394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001009000071021622394790100001004003840038400384003840038
1020440037300000147394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000231394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
102044003729900061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000212394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071021622394790100001004003840038400384003840038
1020440037300000208394072510100100100001001000050057069080400184003740037381083387451010020010000200200004003740037111020110099100100100001000000171021622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400373000198106535206579393531801006311100541911036935719472040298404604046238167423893611200241142232229104044940415101100211091010100001022201287038536122121639880510000104055940557405544055240512
10024403703031110714649680830839335236100761510066221148086572064814040340545405493817750389661149224116172023542405094045212110021109101010000102020206402162239473010000104003840038400384003840038
100244003729900000006139407251001010100001010000505706908140018400834008438130338767100102010000202000040037400371110021109101010000100000006402162239473010000104008540038400384003840038
100244003729900200006139407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100200006402162239473010000104003840038400384003840038
10024400373000000000789394072510010101000010100005057069081400184003740037381303387671001020100002020000400374003711100211091010100001000000126402162239473010000104003840038400384003840038
1002440037299000000019139407251001010100001010000505706908140018400374003738130338767101592010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300000000014739407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003730000000008239407251001010100001010000505706908140018400374003738130338767100102010000202000040037400371110021109101010000100000506402162239473010000104003840038400384003840038
1002440037300000000217039407251002010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
100244003729900000006139407251001010100001010000505706908040018400374003738130338767100102010000202000040037400371110021109101010000100000006402162239473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fmul v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300003421263940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037299100613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038
10204400373000015613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300000000823940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
10024400373000000007263940725100101010000101000050570690804001840084400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000823940725100101010000101000050570690804001840037400373814333876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020200004003740037111002110910101000010000000640216223947310000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  fmul v0.8h, v8.8h, v9.8h
  fmul v1.8h, v8.8h, v9.8h
  fmul v2.8h, v8.8h, v9.8h
  fmul v3.8h, v8.8h, v9.8h
  fmul v4.8h, v8.8h, v9.8h
  fmul v5.8h, v8.8h, v9.8h
  fmul v6.8h, v8.8h, v9.8h
  fmul v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150237422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051106164420037800001002004120041200412004120041
802042004015066422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051105165520037800001002004120041200412004120041
80204200401500422580100100801021118000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051103164520037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051105165420037800001002004120041200412004120041
802042004015001372580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051104164520037800001002004120041200412004120041
80204200401509422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051105165420037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051105163520037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051104165420037800001002004120041200412004120041
802042004015036422580100100800001008000050064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051104163520037800001002004120041200412004120041
80204200401500422580100100800001008012450064000020021200402004099733999880100200800002001600002004020040118020110099100100800001000051105165420037800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500132041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020916752003780000102004120041200412004120041
800242004015000041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716752003780000102004120041200412004120041
800242004015000041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716752003780000102004120041200412004120041
8002420040150000412580010108000010800005064000002002120040200401000531002080010208000020160000200402004011800211091010800001000005020516752003780000102004120041200412004120041
800242004015009041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716772003780000102004120041200412004120041
800242004015009041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716572003780000102004120041200412004120041
8002420040150015041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020516752003780000102004120041200412004120041
80024200401500252041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716752003780000102004120041200412004120041
800242004015000041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020516572003780000102004120041200412004120041
800242004015000041258001010800001080000506400000200212004020040999631002080010208000020160000200402004011800211091010800001000005020716752003780000102004120041200412004120041