Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FNEG (scalar, H)

Test 1: uops

Code:

  fneg h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371524611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fneg h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968625101001001000010010000500284752120018200372003718428718741101002001000820010180200372003711102011009910010010000100011171701600198000100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752120018200372003718428618741101002001000820010008200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715021611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715024611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715039611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715039611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715021611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715021611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715066611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715012611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150101003750268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
10024200371501010060268196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
10024200371501010000268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
1002420037150101004740268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
1002420037150101000026819686251001011100121010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000644111610519786010000102003820038200382003820038
1002420037150101000026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000644101651019786010000102003820038200382003820038
100242003715010100630268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
100242003715010100240268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101119786010000102003820038200382003820038
10024200371501010000268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006441016101019786010000102003820038200382003820038
10024200371501010015026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000000644101610519786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fneg h0, h8
  fneg h1, h8
  fneg h2, h8
  fneg h3, h8
  fneg h4, h8
  fneg h5, h8
  fneg h6, h8
  fneg h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015002052580208100801001008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111513416020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
802042003815030292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
802042003815021292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064072420019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
802042003815021292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000111511816020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501503303925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100001502000116112003580000102003920039200392003920039
800242003815045603925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100030502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
800242003815038103925800101080000108000050640724102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
800242003815024903925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000102001920038200389996310018800102080000208000020038200381180021109101080000100000502000116112003580000102003920039200392003920039