Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FNEG (vector, 2S)

Test 1: uops

Code:

  fneg v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371505341686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150821686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fneg v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001003007101161119791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010022307101161119791100001002003820038200382003820038
102042003715001241968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007341161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715012771968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010054307101161119791100001002003820038200382003820038
10204200371500841968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500821968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500841968625101001001000010010000500284752112001802003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500214196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640316221978610000102003820038200382003820038
10024200371500369196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101004810100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000669216221978610000102003820038200382003820038
10024200371500438196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001010640216221978610000102003820038200382003820038
1002420037150010319686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000103715640216221978610000102003820038200382003820038
1002420037150061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500103196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038
10024200371500147196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fneg v0.2s, v8.2s
  fneg v1.2s, v8.2s
  fneg v2.2s, v8.2s
  fneg v3.2s, v8.2s
  fneg v4.2s, v8.2s
  fneg v5.2s, v8.2s
  fneg v6.2s, v8.2s
  fneg v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150000001362580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118116120035800001002003920039200392003920039
8020420038150000002032580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150000001172580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001001001115118016020035800001002003920039200392003920039
802042003815000000502580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150000003212580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016120035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016120035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016020035800001002003920039200392003920039
8020420038150000005002580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000001115118016120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000030502000116112008780000102003920039200392003920039
800242003815039258001010800001080390506400001020019200382003899963100188001020800002080000200382003811800211091010800001000000502054116122003580000102003920039200392003920039
800242003815039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000000502000116132003580000102003920039200392003920039
8002420038150209258001010800001080000506400000520019200382003899963100188001020800002080000200382003811800211091010800001000000502054116112003580000102003920039200392003920039
800242003815060258001010800001080000506400001020019200382003899963100188001020800002080000200382003811800211091010800001002000502000116142003580000102003920039200392003920039
800242003815039258001010800001080000506400000520019200382003899963100188001020800002080000200382003811800211091010800001000000502054116112003580000102003920039200392003920039
8002420038150150258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001001000502000116432003580000102003920039200392003920039
800242003815062258001010800001080000506400000020019200382003899963100188001020800002080132200382034411800211091010800001000000502054116122003580000102003920039200872003920039
800242003815081258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001000000502000116122003580000102003920039200392003920039
800242003815060258001010800001080000506400001520019200382003899963100188001020800002080000200382003811800211091010800001001000502000116122003580000102003920039200392003920039