Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FNEG (vector, 4S)

Test 1: uops

Code:

  fneg v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000752161121786100020382038203820382038
1004203715025116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000751162121786100020382038203820382038
100420371636116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
1004203715426116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
100420371608216862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
1004203715576116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000751161121786100020382038203820382038

Test 2: Latency 1->2

Code:

  fneg v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500147196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007102161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000027101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500170196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371490149196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150084196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500124196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000158196862510010101000012100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000149196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420084150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037149000000061196862510010101000010100005028475212001820037200371844331876710010201000020100002003720037111002110910101000010000000006402163319786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fneg v0.4s, v8.4s
  fneg v1.4s, v8.4s
  fneg v2.4s, v8.4s
  fneg v3.4s, v8.4s
  fneg v4.4s, v8.4s
  fneg v5.4s, v8.4s
  fneg v6.4s, v8.4s
  fneg v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118161120035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118161120035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
80204200381500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118160020035800001002003920039200392003920039
802042003815001242580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001001115118161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500032625800101080000108000050640000020019020038200389996310018800102080000208000020038200881180021109101080000100645037021630122003580000102003920039200392003920039
80024200381501031325800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600112003580000102003920039200392003920039
80024200381501123925800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600112003580000102003920039200392003920039
8002420038150008125800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600312003580000102003920039200392003920039
80024200381500028325801031080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020031600212015080000102003920039200392003920039
8002420038150006225800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600122003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600212003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011610112003580000102003920039200392003920039
80024200381501023225800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020011600112003580000102003920039200392003920039
8002420038150006025800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020411600112003580000102003920039200392003920039