Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FNMADD (scalar, D)

Test 1: uops

Code:

  fnmadd d0, d0, d1, d2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073216113473100040384038403840384038
1004403731017834072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373106134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000373116113473100040384038403840384038
100440373106134072510001000100053190814018403740373258338951000100030004037403711100110000373116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
100440373106134072510001000100053190804018403740373258338951000100030004037403711100110000367073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  fnmadd d0, d0, d1, d2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730000000726394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071002162239479100001004003840038400384003840038
10204400373000000089394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162239479100001004003840038400384003840038
10204400372990000061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012164239479100001004003840038400384008540038
10204400373000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162339479100001004003840038400384003840038
102044003730000000782394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162239479100001004003840038400384003840038
10204400372990000061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162339479100001004003840038400384003840038
10204400373000000061394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001001071012162239479100001004003840038400384003840038
102044003730000000105394072510100100100001001000050057069080400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162339479100001004003840038400384003840038
10204400373000000061394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000071212162239479100001004003840038400384003840038
10204400372990000061394072510100100100001001000050057069081400184003740037381083387451010020010000200300004003740037111020110099100100100001000071012162239479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003729900006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216263947310000104003840038400384003840038
1002440037299000053639407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216233947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216223947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000640216323947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100001640216233947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000640216233947310000104003840038400384003840038
100244003730000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000640216223947310000104003840038400384003840038

Test 3: Latency 1->3

Code:

  fnmadd d0, d1, d0, d2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000000000006139407251010010010000100100005005706908040018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633394790100001004003840038400384003840038
102044003730000000000061394072510100100100001001000050057069080400180400374003738108338745101002001000020030000400374003711102011009910001001000010000049000710131633394790100001004003840038400384003840038
10204400373000000000006139407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633394790100001004003840038400384003840038
10204400373000000000006139407251010010010000100100005005706908040018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131643394790100001004003840038400384003840038
10204400372990000009006139407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633394790100001004003840038400384003840038
10204400373000000000006139407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633394790100001004003840038400384003840038
10204400373000000000006139407251010010010006100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633395530100001004003840038400384003840038
10204400373000000000006139407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000712131643394790100001004003840038400384003840038
10204400372990000000006139407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710131633394790100001004003840038400384003840038
102044003730000000000072639407251010010010000100100005005706908140018040037400373810833874510100200100002003000040037400371110201100991000100100001000000000710141634394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640316323947310000104003840038400384003840038
10024400373000013261394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069081400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
1002440037300000726394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000061393892510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400372990010861394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
100244003730000061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038
10024400373000741061394072510010101000010100005057069080400184003740037381303387671001020100002030000400374003711100211091010100001000640216223947310000104003840038400384003840038

Test 4: Latency 1->4

Code:

  fnmadd d0, d1, d2, d0
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000330613940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
10204400372990006139407251010010010000100100005005706908400184003740037381080338745101002001000020030000400374003711102011009910010010000100041200710121622394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
1020440037300000613940725101001021000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840085400384003840038
1020440037299000613940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
10204400373000004603940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
1020440037300000613940725101001001000010010000500570690840022400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
10204400373000009633940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010000000710121622394790100001004003840038400384003840038
1020440037299000613940725101001001000010010000500570690840018400374003738108033874510100200100002003000040037400371110201100991001001000010070000710121622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
10024400372990000025139407251001010100001010000505706908140018400374003738150338767100102010000203000040037400371110021109101010000100000306402162239473010000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037299100006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037299000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000016402162239473010000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440084300000008239407251001010100001010000505706908040018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018400374003738130338767100102010000203000040037400371110021109101010000100000006402162239473010000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  fnmadd d0, d8, d9, d10
  fnmadd d1, d8, d9, d10
  fnmadd d2, d8, d9, d10
  fnmadd d3, d8, d9, d10
  fnmadd d4, d8, d9, d10
  fnmadd d5, d8, d9, d10
  fnmadd d6, d8, d9, d10
  fnmadd d7, d8, d9, d10
  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915000042258010010080000100800005006400001200212004020040997339998801002008000020024000020040200401180201100991001008000010010051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400001200212004020040997339998801002008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400001200212004020040997339998802162008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400001200212004020040997339998801002008000020024000020040200401180201100991001008000010010051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400000200212004020040997339998801002008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041
80204200401500004225801001008000010080000500640000020021200402004099733999880100200800002002400002004020040118020110099100100800001003207251101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400000200212004020040997339998801002008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400000200212004020040997339998801002008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400000200212004020040997339998801002008000020024000020040200401180201100991001008000010010351101161120037800001002004120041200412004120041
802042004015000042258010010080000100800005006400000200212004020040997339998801002008000020024000020040200401180201100991001008000010000051101161120037800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500041258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000105020916532003780000102004120041200412004120041
80024200401500041258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000205020316352003780000102004120041200412004120041
80024200401500041258001010800001080000506400001200212009120040999631002080010208000020240000200402004011800211091010800001000035020516452003780000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020240000200402004011800211091010800001000005020316462003780000102004120041200412004120041
800242004015000326258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001001005020316352003780000102004120041200412004120041
80024200401500041258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000105020616462003780000102004120041200412004120041
80024200401500041258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000205020516532003780000102004120041200412004120041
80024200401500041258001010800001080000506400001200212004020040999631002080010208000020240000200402004011800211091010800001000005020516532003780000102004120041200412004120041
80024200401500041258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000005020516362003780000102004120041200412004120041
8002420040150001110258001010800001080000506400000200212004020040999631002080010208000020240000200402004011800211091010800001000005020316352003780000102004120041200412004120041