Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPE (vector, 4S)

Test 1: uops

Code:

  frecpe v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
1004303722061190025100010001000104451301830373037273832895100010001000303730371110011000011173116112919100030383038303830383038
10043037220611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
100430372221611900251000100010001044513018303730372738328951000100010003037303711100110001073116112919100030383038303830383038
10043037230611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
10043037230611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
10043037220611900251000100010001046123018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
10043037220611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
10043037220611900251000100010001044513018303730372738328951000100010003037303711100110000073116112919100030383038303830383038
10043037220611900251000100010001044513018303730372738328951000100010003037303711100110001073116112919100030383038303830383038

Test 2: Latency 1->2

Code:

  frecpe v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000006119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100010071021622299190100001003003830038300383003830038
10204300372250003606119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
102043003722500081044119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
10204300372250000886119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
1020430037224000006119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
1020430037225000006119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
1020430037225000006119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003721102011009910010010000100000071021622299190100001003003830038300383003830038
1020430037225000006119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
10204300372240400019919900251010010010000100100005001067451130018300373003728588328745101002021000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038
1020430037225000006119900251010010010000100100005001067451030090300853003728588328745101002001000020010000300373003711102011009910010010000100000071021622299190100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373008421100211091010100001000000640216222991910000103003830038300383003830038
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830083
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038
1002430037224000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038
1002430037224000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640416222991910000103003830038300383003830038
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038
1002430037225000061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038
1002430037225000061199002510010101000010100005010674511300183003730037286103287671005220100002010000300373008411100211091010100001000000640216222991910000103003830038300383003830038
10024300372250015061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000000640216222991910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  frecpe v0.4s, v8.4s
  frecpe v1.4s, v8.4s
  frecpe v2.4s, v8.4s
  frecpe v3.4s, v8.4s
  frecpe v4.4s, v8.4s
  frecpe v5.4s, v8.4s
  frecpe v6.4s, v8.4s
  frecpe v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020480039600003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039599003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039599003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039600003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039600003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080204800408004080040
8020480039599008125801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039599003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480088599003925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
8020480039599063925801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040
80204800395990070425801001008000010080000500640000180020800398003969971670021801002008000820080008800398003911802011009910010080000100000000111511701680036800001008004080040800408004080040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800248003959900071525800101080000108000050640000180020800398003969986037001980010208000020800008003980039118002110910108000010000050200261608128003480000108004080040800408004080040
80024800395990037152580010108000010800005064000018002080039800396998603700198001020800002080000800398003911800211091010800001000005020012160698003480000108004080040800408004080040
80024800396000007152580010108000010800005064000008002080039800396998603700198001020800002080000800398003911800211091010800001000005020010160998003480000108004080040800408004080040
80024800395990007156180034108000010800005064000008002080039800396998603700198001020800002080000800398003911800211091010800001000005020010160888003480000108004080040800408004080040
800248003960000050258001010800001080000506400000800208003980039699860370019800102080000208000080039800391180021109101080000100000502008160978003480000108004080040800408004080040
800248003960000050258001010800001080000506400001800208003980039699860370019800102080000208004480039800391180021109101080000100000502009160968003480000108004080040800408004080040
800248003960000050258001010800001080000506400001800208003980039699860370019800102080000208000080039800391180021109101080000100000502008160978003480000108004080040800408004080040
8002480039599000715258001010800001080000506400001800208003980039699860370019800102080000208000080039800391180021109101080000100000502008160998003480000108004080040800408004080040
8002480039600000502580010108000010800005064000018002080039800396998603700198001020800002080000800398003911800211091010800001000005020081601068003480000108004080040800408004080040
8002480039600000502580010108000010800005064000008002080039800396998603700198001020800002080000800398003911800211091010800001000015020091608118003480000108004080040800408004080040