Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPS (scalar, H)

Test 1: uops

Code:

  frecps h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10044037300906134072510001000100053190804018403740373258338951000100020004037403711100110007573116113473100040384038403840384038
10044037300006134072510001000100053190804018403740373258338951000100020004037403711100110008473116113473100040384038403840384038
1004403731000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730000613407251000100010005319080401840834037325833895100010002000403740371110011000073116113473100040854038403840384038
1004403730190613407251000100010005319081401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730000613407251000100010005319081401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730000613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038
1004403730000613407251000100010005319081405440374037325833895100010002000403740371110011000073116113473100040384038403840384038
10044037300240613407251000100010005319080401840374037325833895100010002000403740371110011000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  frecps h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000906139407441010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730003606139407251010010010000100100005005706908140018400844008538108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730003006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
1020440037299012010339407251013412810000100100005005706908140018400374003738108338745101002001000020020000400854003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000096339407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
10204400373000006139407251010010010000100100005005706908140018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730002106139407251010010010000100100005005706908140018400854003738108338745101002001000020020000400374003711102011009910010010000100037101331139479100001004003840038400864003840038
10204400843011393072639407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100107101161139479100001004003840038400384003840038
10204400372990006139407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
1020440181300057096739407251010010010000100100005005706908040018400374003738108338745101002001000020020000400374003711102011009910010010000100007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400372990002323940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100036404162239473010000104003840038400384003840038
10024400372990390613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400372990510613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037300090613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037300060613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003729903048203940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299042905363940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
1002440037299024352613940725100101010000101000050570690840018400374008438130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10025400373000180613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400372990240613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  frecps h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400372990061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
102044003730000726394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
1020440037300935261394072510100100100001001000050057069081400184003740037381113387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
102044003730021061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740085111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400372996061394072510100100100001001000050057069081400534003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038
10204400373000061394072510100100100001001000050057069081400184003740037381083387451010020010000200200004003740037111020110099100100100001000000071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037299000510613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
10024400373000004920613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000012015133940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110022109101010000100006402163239473010000104003840038400384003840038
100244003729900000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003729900000613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038
100244003730000060613940725100101010000101000050570690840018400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  frecps h0, h8, h9
  frecps h1, h8, h9
  frecps h2, h8, h9
  frecps h3, h8, h9
  frecps h4, h8, h9
  frecps h5, h8, h9
  frecps h6, h8, h9
  frecps h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015004225801001008000010080000500640000200212004020040997303999880100200800002001600002004020040118020110099100100800001000048051103161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
80204200401506422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100100051101161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
80204200401500422580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100000051101161120037800001002004120041200412004120041
802042004015004222580100100800001008000050064000020021200402004099730399988010020080000200160000200402004011802011009910010080000100100051101161120037800001002004120041200412004120041
802042004015004225801001008000010080000500640000200212004020040997303999880100200800002001600002004020040118020110099100100800001002603051101161120037800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015001100083258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100160050205163520037080000102004120041200412004120041
8002420040150000000412580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001003590050206165320037080000102004120041200412004120041
80024200401500000129041258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100090050205165320037080000102004120248200412004120041
8002420040150100008841258001010800001080000506400000120021200402004099963100208001020802112016000020040200401180021109101080000100300050205166520037080000102004120041200412004120041
8002420040150000000412580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001003000050203163620037080000102004120041200412004120041
8002420040150000300412580010108000010800005064000001200212004020040999631002080010208000020160000200402004011800211091010800001005700050205165320037080000102004120041200412004120041
800242004015000000041258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100090050203163520037080000102004120041200412004120041
800242004015000000046258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100230050204165320037080000102004120041200412004120041
8002420040150000000232258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100230050203165320037080000102004120041200412004120041
800242004015000000083258001010800001080000506400000120021200402004099963100208001020800002016000020040200401180021109101080000100100050205165320037080000102024820041200412004120041