Firestorm: FRECPS (scalar, S) measurements

Code:

  frecps s0, s0, s1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	2	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	156	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	39	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	108	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	27	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	195	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	21	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	9	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	3	82	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	240	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	4018	4037	4037	3258	3	3895	1000	1000	2000	4037	4037	1	1	1001	1000	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->2

Code:

  frecps s0, s0, s1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39549	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	626	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40229	40038	40038	40038
10204	40037	300	1	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	127	10000	626	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20348	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	17	5	5	39479	0	10000	100	40134	40038	40038	40038	40038
10204	40037	299	0	1	0	1	0	0	294	0	0	1147	39335	141	10194	144	10054	147	11332	785	5718076	0	40333	40425	40321	38139	44	38889	11484	232	11490	225	21662	40454	40422	10	1	10201	100	99	100	100	10000	100	0	3	1	2	32348	2	0	890	3	102	6	6	39802	37	10000	100	40465	40421	40466	40417	40416
10204	40471	303	0	1	1	1	9	10	1200	792	0	7299	39371	204	10204	154	10054	152	10444	746	5719472	0	40158	40504	40467	38142	41	38911	11485	230	11490	230	22908	40468	40467	5	1	10201	100	99	100	100	10000	100	2	3	1	2	32388	0	0	932	3	112	2	4	39694	30	10000	100	40465	40658	40509	40518	40515
10204	40468	303	0	0	0	0	0	0	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	0	0	61	39407	25	10125	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40084	1	1	10021	10	9	10	10	10000	10	15	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->3

Code:

  frecps s0, s1, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	24	0	1593	39407	25	10100	100	10000	100	10000	500	5707439	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	1323	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	1285	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	642	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	20000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	24	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	669	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1127	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	536	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	1839	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	1279	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	20000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40086

Test 4: throughput

Count: 8

Code:

  frecps s0, s8, s9
  frecps s1, s8, s9
  frecps s2, s8, s9
  frecps s3, s8, s9
  frecps s4, s8, s9
  frecps s5, s8, s9
  frecps s6, s8, s9
  frecps s7, s8, s9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20058	150	0	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	2	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	656	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	1	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9997	80125	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	3	0	0	42	25	80125	125	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9997	80125	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	107	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	64	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80125	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	1	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041
80204	20040	150	0	0	0	0	0	0	0	0	0	42	25	80100	100	80000	100	80000	500	640000	0	20021	20040	20040	9973	3	9998	80100	200	80000	200	160000	20040	20040	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	20037	0	80000	100	20041	20041	20041	20041	20041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20049	150	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	17	16	0	16	15	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20091	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	16	16	0	11	18	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	16	16	0	16	16	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	18	16	0	16	17	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	17	16	0	17	17	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	83	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	16	16	0	16	16	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	508	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	18	16	0	17	16	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	150	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	3	5020	0	17	16	0	17	17	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	1	20021	20040	20040	9996	3	10020	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	16	16	0	17	16	20037	80000	10	20041	20041	20041	20041	20041
80024	20040	150	0	41	25	80010	10	80000	10	80000	50	640000	0	20021	20040	20040	9996	3	10047	80010	20	80000	20	160000	20040	20040	1	1	80021	10	9	10	10	80000	10	36	3	5020	0	16	16	0	16	16	20037	80000	10	20041	20041	20041	20041	20041

FRECPS (scalar, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations