Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FRECPS (vector, 4H)

Test 1: uops

Code:

  frecps v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403730012434072510001000100053190814018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190814018403740373258338951000100020004037408511100110000073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373106134072510001000100053190804018403740373258338951000100020004037403711100110001073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
1004403730306134072510001000100053190814018403740373258338951000100020004037403711100110000073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110001073116113473100040384038403840384038
100440373006134072510001000100053190804018403740373258338951000100020004037403711100110000073116113473100040384038403840384038

Test 2: Latency 1->2

Code:

  frecps v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e1f3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020440037300006139407025101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373000094339407225101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007103401139479100001004003840038400384003840038
10204400372992131086139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300006139407025101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400372990025139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300006139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300006139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037299006139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300006139407025101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037300006139407025101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400372990061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100036402162239473010000104003840038400384003840038
1002440037299006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010001236402322239473010000104003840038400384003840038
1002440037299006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010001176402162239473010000104003840038400384003840038
100244003730000613940725100101010000101000050570690814001804003740037381303387671001020100002020000400374003711100211091010100001000126402162239473210000104003840038400384003840038
100244003730000893940725100101010000101000050570690804001804003740037381303387671001020100002020000400374003711100211091010100001006276402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100006402162239473010000104003840038400384003840083
1002440037300006139407251001010100001010000505706908040018040037400373813033876710010201000020200004003740037111002110910101000010001386402162239473010000104003840038400384003840038
1002440037299003463940725100101010000101000050570690804001804003740037381303387671001020100002020000400374003711100211091010100001000786402162239473010000104003840038400384003840038
10024400373000061394072510010101000010100005057069080400180400374003738130338767100102010000202000040037400371110021109101010000100096402162239473010000104003840038400384003840038
100244003730000613940725100101010000101000050570690804001804003740037381303387671001020100002020000400374003711100211091010100001002145476402162239473010000104003840038400384003840038

Test 3: Latency 1->3

Code:

  frecps v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000613940725101001001000010010000500570690814001840133400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373001613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003730007263940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
1020440037299014933940725101001001000010410000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003729907263940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010001007101161139479100001004003840038400384003840038
10204400823000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
10204400373000613940725101001001000010010000500570690814001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038
102044003730012613940725101001001000010010000500570690804001840037400373810833874510100200100002002000040037400371110201100991001001000010000007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024400372990000210394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000170394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000016402161239473010000104003840038400384003840038
10024400373000000208394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000124394072510010101000010100005057069080400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000061394072510010101000010100005057069080400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400372990000189394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
10024400373000000124394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000061394072510010101000010100005057069081400180400374003738130033876710010201000020200004003740037111002110910101000010000006402162239473010000104003840038400384003840038

Test 4: throughput

Count: 8

Code:

  frecps v0.4h, v8.4h, v9.4h
  frecps v1.4h, v8.4h, v9.4h
  frecps v2.4h, v8.4h, v9.4h
  frecps v3.4h, v8.4h, v9.4h
  frecps v4.4h, v8.4h, v9.4h
  frecps v5.4h, v8.4h, v9.4h
  frecps v6.4h, v8.4h, v9.4h
  frecps v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150054825801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511041622200370800001002004120041200412004120041
802042004015004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
802042004015008425801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
802042004015006325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
802042004015006325801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
802042004015004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
8020420040150013225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021623200370800001002004120041200412004120041
8020420040150021425801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041
8020420040150057025801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511031622200370800001002004120041200412004120041
802042004015004225801001008000010080000500640000120021200402004099733999880100200800002001600002004020040118020110099100100800001000511021622200370800001002004120041200412004120041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004915004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015004125800101080000108000050640000020021200402004099963100208001020800002016000020040200401180021109101080000101005020116112003780000102004120041200412004120041
80024200401507816625800101080000108000050640000020021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412011520041
8002420040150012525800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015006425800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015008325800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041
800242004015004125800101080000108000050640000120021200402004099963100208001020800002016000020040200401180021109101080000100005020116112003780000102004120041200412004120041